✦ LIBER ✦

Simulation and verification of associative processor arrays

✍ Scribed by A.W.G. Duller; R. Storer

Publisher: Elsevier Science
Year: 1992
Tongue: English
Weight: 726 KB
Volume: 18
Category: Article
ISSN: 0167-8191
DOI: 10.1016/0167-8191(92)90129-u

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Simulation of condensed phases using the

Simulation of condensed phases using the Distributed Array Processor

✍ Michael P. Allen 📂 Article 📅 1993 🏛 Springer 🌐 English ⚖ 940 KB

A fast processor for 3-d device simulati

A fast processor for 3-d device simulation using systolic arrays

✍ Takashi Naritomi; Hirotomo Aso; Masayuki Kimura 📂 Article 📅 1991 🏛 John Wiley and Sons 🌐 English ⚖ 661 KB

Simulation of binary tree and pyramid ar

Simulation of binary tree and pyramid architectures on optical reconfigurable array processors

✍ M. Hossain; S. Ghanta 📂 Article 📅 1994 🏛 Elsevier Science 🌐 English ⚖ 949 KB

Compiling a vector and array processing

Compiling a vector and array processing language for an associative processor

✍ Peter Brezany; Viera Sipkova 📂 Article 📅 1992 🏛 Elsevier Science ⚖ 216 KB

Costs of vector and array processor soft

Costs of vector and array processor software development: A specific example from biological simulation

✍ C.J. Cartledge; M. Narotam; N.D.H. Ross; J.B. Slater 📂 Article 📅 1982 🏛 Elsevier Science 🌐 English ⚖ 148 KB

A biological simulation problem has been adopted and run and improved on a number of different machines. Particular attention was paid to the man power costs associated with mounting.

Hierachical modeling and simulation of p

Hierachical modeling and simulation of processor architectures

✍ Willem Jan Withagen; Rob Takken 📂 Article 📅 1993 🏛 Elsevier Science ⚖ 303 KB