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Short-circuit power driven gate sizing technique for reducing power dissipation

โœ Scribed by Uming Ko; Balsara, P.T.


Book ID
115470157
Publisher
IEEE
Year
1995
Tongue
English
Weight
615 KB
Volume
3
Category
Article
ISSN
1063-8210

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An e$cient analytical method for calculating the propagation delay and the short-circuit power dissipation of CMOS gates is introduced in this paper. Key factors that determine the operation of a gate, such as the di!erent modes of operation of serially connected transistors, the starting point of c