Selective ion implantation to reduce power consumption in MOS integrated circuits

[Lecture Notes in Computer Science] Inte

[Lecture Notes in Computer Science] Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation Volume 6448 || Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random VT Variations on Timing

✍ van Leuken, René; Sicard, Gilles 📂 Article 📅 2011 🏛 Springer Berlin Heidelberg 🌐 English ⚖ 714 KB

This book constitutes the refereed proceedings of the 20th International Conference on Integrated Circuit and System Design, PATMOS 2010, held in Grenoble, France, in September 2010. The 24 revised full papers presented and the 9 extended abstracts were carefully reviewed and are organized in topica