[Lecture Notes in Computer Science] Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation Volume 6448 || Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random VT Variations on Timing

✍ Scribed by van Leuken, René; Sicard, Gilles

• Book ID: 118178376
• Publisher: Springer Berlin Heidelberg
• Year: 2011
• Tongue: English
• Weight: 714 KB
• Edition: 1
• Category: Article
• ISBN: 3642177522
• DOI: 10.1007/978-3-642-17752-1_17

✦ Synopsis

This book constitutes the refereed proceedings of the 20th International Conference on Integrated Circuit and System Design, PATMOS 2010, held in Grenoble, France, in September 2010. The 24 revised full papers presented and the 9 extended abstracts were carefully reviewed and are organized in topical sections on design flows; circuit techniques; low power circuits; self-timed circuits; process variation; high-level modeling of poweraware heterogeneous designs in SystemC-AMS; and minalogic.