A statistical description of the global performance of on-chip spiral inductors, based on extensive measurement is presented. These inductors were fabricated with different turn numbers or track lengths/track widths, but with the same spacing. From the S parameters measured using a de-embedding tech
Scalable distributed-capacitance model for silicon on-chip spiral inductors
✍ Scribed by Fengyi Huang; Jingxue Lu; Nan Jiang
- Publisher
- John Wiley and Sons
- Year
- 2006
- Tongue
- English
- Weight
- 184 KB
- Volume
- 48
- Category
- Article
- ISSN
- 0895-2477
No coin nor oath required. For personal study only.
✦ Synopsis
Abstract
We present physics‐based modeling for silicon on‐chip spiral inductors, taking into account the coupling capacitance between metal spirals. The coupling capacitance C~p~ is calculated using a distributed‐capacitance model based on finite‐element analysis. As demonstrated for a series of inductors with the number of turns ranging from 2.5 to 6.5 fabricated in a 0.18‐μm CMOS technology, the current model provides simulation results for the quality factor Q, the S‐parameter, and the self‐resonance frequency f~SR~ that are in good agreement with the measurements without any fitting parameters. © 2006 Wiley Periodicals, Inc. Microwave Opt Technol Lett 48: 1423–1427, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21642
📜 SIMILAR VOLUMES