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RISC, a microprocessor architecture for GaAs technology

✍ Scribed by E.R Fox; K.J Kiefer; R.F Vangen; S.P Whalen

Book ID
107910222
Publisher
Elsevier Science
Year
1988
Weight
522 KB
Volume
22
Category
Article
ISSN
0165-6074

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MARS: a RISC-based architecture for Lisp
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✍ Hung-Chang Lee; Feipei Lai; Jenn-Yuan Tsai; Tai-Ming Parng πŸ“‚ Article πŸ“… 1990 πŸ› Elsevier Science 🌐 English βš– 952 KB

A RISC-based chip set architecture for Lisp is presented in this paper. This architecture contains an instruction fetch unit (IFU) and three processing units--integer processing unit (IPU), floating-point processing unit (FPU), and list processing unit (LPU). The IFU feeds instructions to the proces