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Resistor-loaded high-speed sense circuit for Josephson memory

โœ Scribed by Fujita, S.; Yamamoto, M.; Miyahara, K.; Nakanishi, T.


Book ID
114595108
Publisher
IEEE
Year
1985
Tongue
English
Weight
504 KB
Volume
32
Category
Article
ISSN
0018-9383

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High-speed sense circuit techniques for
โœ Akihiko Emori; Kunihiko Suzuki; Seigoh Yukutake; Sadayuki Ookuma; Kinya Mitumoto ๐Ÿ“‚ Article ๐Ÿ“… 1998 ๐Ÿ› John Wiley and Sons ๐ŸŒ English โš– 152 KB

This paper describes a high-speed and low-power 1-Mbit BiCMOS cache SRAM sense circuit fabricated using a 0.5-mm BiCMOS process technology. By using the quasi-6 module structure, switching between 18-and 36-bit output can be carried out without access delay. Because of the development of a sense cir