High-speed sense circuit techniques for a 1-mbit BiCMOS cache SRAM

✍ Scribed by Akihiko Emori; Kunihiko Suzuki; Seigoh Yukutake; Sadayuki Ookuma; Kinya Mitumoto; Takashi Akioka; Masahiro Iwamura; Noboru Akiyama

• Book ID: 101292896
• Publisher: John Wiley and Sons
• Year: 1998
• Tongue: English
• Weight: 152 KB
• Volume: 81
• Category: Article
• ISSN: 8756-663X
• DOI: 10.1002/(sici)1520-6432(199808)81:8<55::aid-ecjb8>3.0.co;2-0

✦ Synopsis

This paper describes a high-speed and low-power 1-Mbit BiCMOS cache SRAM sense circuit fabricated using a 0.5-mm BiCMOS process technology. By using the quasi-6 module structure, switching between 18-and 36-bit output can be carried out without access delay. Because of the development of a sense circuit with a low-amplitude current amplifier and equalization/write-recovery circuit, the sense delay is 0.8 ns, which is 50% faster than the conventional common collector configuration. Using this