<em>Principles of Verifiable RTL Design: A Functional Coding Style</em><em>Supporting Verification Processes in Verilog</em> explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. This cooperation can return an order of ma
Principles of Verifiable RTL Design: A functional coding style supporting verification processes in Verilog
β Scribed by Lionel Bening, Harry Foster (auth.)
- Publisher
- Springer US
- Year
- 2002
- Tongue
- English
- Leaves
- 296
- Edition
- 2
- Category
- Library
No coin nor oath required. For personal study only.
β¦ Synopsis
System designers, computer scientists and engineers have c- tinuously invented and employed notations for modeling, speci- ing, simulating, documenting, communicating, teaching, verifying and controlling the designs of digital systems. Initially these s- tems were represented via electronic and fabrication details. F- lowing C. E. Shannonβs revelation of 1948, logic diagrams and Boolean equations were used to represent digital systems in a fa- ion that de-emphasized electronic and fabrication detail while revealing logical behavior. A small number of circuits were made available to remove the abstraction of these representations when it was desirable to do so. As system complexity grew, block diagrams, timing charts, sequence charts, and other graphic and symbolic notations were found to be useful in summarizing the gross features of a system and describing how it operated. In addition, it always seemed necessary or appropriate to augment these documents with lengthy verbal descriptions in a natural language. While each notation was, and still is, a perfectly valid means of expressing a design, lack of standardization, conciseness, and f- mal definitions interfered with communication and the understa- ing between groups of people using different notations. This problem was recognized early and formal languages began to evolve in the 1950s when I. S. Reed discovered that flip-flop input equations were equivalent to a register transfer equation, and that xvi tor-like notation. Expanding these concepts Reed developed a no- tion that became known as a Register Transfer Language (RTL).
β¦ Table of Contents
Introduction....Pages 1-8
The Verification Process....Pages 9-21
Coverage, Events and Assertions....Pages 23-42
RTL Methodology Basics....Pages 43-68
RTL Logic Simulation....Pages 69-101
RTL Formal Verification....Pages 103-129
Verifiable RTL Style....Pages 131-172
The Bad Stuff....Pages 173-208
Verifiable RTL Tutorial....Pages 209-238
Principles of Verifiable RTL Design....Pages 239-245
β¦ Subjects
Circuits and Systems; Computer Hardware; Computer-Aided Engineering (CAD, CAE) and Design; Electronic and Computer Engineering
π SIMILAR VOLUMES
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