Silicon-on insulator (SOI) wafers, consisting of 22 lm thick p-type silicon epitaxial layer grown on 280 lm thick n-type (1 1 1) silicon substrate, were electrochemically etched in hydrofluoric acid (HF) to produce porous silicon (PS) samples. The pores of different size and different depth were obt
Preparation and electrical characterization of low-dimensional net structures made out of GaAs epitaxial layers
✍ Scribed by L.V Govor; M Goldbach; I.A Bashmakov; J Parisi
- Publisher
- Elsevier Science
- Year
- 1999
- Tongue
- English
- Weight
- 641 KB
- Volume
- 261
- Category
- Article
- ISSN
- 0375-9601
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✦ Synopsis
The transport properties of low-dimensional patterned semiconductors exhibit interesting phenomena. In this paper, we report on the preparation and electric characterization of mesoscopic GaAs nets which are obtained by Ar-ion etching with a polymer net as mask. The diameter of the meshes is about 1 mm and the thickness of the webs ranges around 50 nm to 100 nm. In a wide low-temperature regime up to 260 K, we find variable range hopping in two dimensions with a nearly constant density of states of the defect band. The absolute values obtained by an adaptation of the local activation energy to predictions of theory are in good agreement with those reported in literature on thin bulk material. We also analyzed the nonlinear voltage dependence of the differential conductivity by percolation theory. The onset of nonlinearity can be described by a threshold, i.e., a critical current. Between the local activation energy and the critical current, a good correlation of the different temperature regimes is found for which a transport mechanism is valid.
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