Preface
Structure of This Book
Acknowledgments
Contents
About the Authors
Part I Introduction to FPGA Technology and VHDL Language
1 Introduction to Field Programmable Gate Arrays (FPGA)
1.1 Introduction to FPGA
1.2 FPGA Architecture
1.2.1 General Structure of an FPGA Circuit
1.2.2 FPGA Routing Architectures
1.3 ASIC Versus FPGA Comparison
1.4 Design Methodology
1.4.1 Design Entry
1.4.2 Synthesis
1.4.3 Implementation and Programming
1.4.4 Design Tools
1.5 Summary
2 Basic VHDL Concepts
2.1 Introduction to Hardware Description Language
2.2 VHDL Design Units
2.2.1 Libraries and Packages
2.2.2 Entity
2.2.3 Architecture
2.3 VHDL Code Instructions
2.3.1 Concurrent Instructions
2.3.2 Sequential Instructions
2.4 Test Bench
2.5 Syntax Summary
2.5.1 Comments
2.5.2 Signal, Variables and Constants
2.5.3 Array
2.5.4 Operators
2.5.5 Attributes
2.6 Summary
Part II Design Digital Circuits (Simulation and Implementation on FPGA)
3 Combinational Logic Circuits
3.1 Introduction
3.2 Arithmetic Circuits
3.2.1 1-Bit Half Adder
3.2.2 1-Bit Full Adder
3.2.3 4-Bit Ripple Carry Adder
3.2.4 4-Bit Adder-Subtractor
3.3 Multiplexers
3.3.1 2-to-1 Multiplexer
3.3.2 4-to-1 Multiplexer
3.3.3 8-to-1 Multiplexer
3.4 Demultiplexer
3.4.1 1-to-4 Demultiplexer
3.4.2 1-to-8 Demultiplexer
3.5 Decoder
3.5.1 2-To-4 Decoder
3.5.2 3-to-8 Decoder
3.5.3 BCD-To-Decimal Decoder
3.6 Encoder
3.6.1 Binary Encoder
3.6.2 Priority Encoder
3.7 Summary
4 Sequential Logic Circuits
4.1 Introduction
4.2 D Flip-Flop
4.2.1 D Flip-Flop with Synchronous Reset
4.2.2 D Flip-Flop with Asynchronous Reset
4.2.3 Application of D Flip-Flop to Build a Clock Divider
4.2.4 Implementation and Validation on FPGA Platform
4.3 Registers
4.3.1 Serial-In Parallel-Out (SIPO) Shift Register
4.3.2 Serial-In Serial-Out (SISO) Shift Register
4.3.3 Parallel-In Parallel-Out (PIPO) Shift Register
4.3.4 Parallel-In Serial-Out (PISO) Shift Register
4.4 Counters
4.4.1 Asynchronous Counter
4.4.2 Synchronous Counter
4.4.3 Ring Counter
4.4.4 Johnson Counter
4.5 Summary
5 Finite State Machines
5.1 Introduction
5.2 Moore Machine
5.3 Mealy Machine
5.4 VHDL Implementation for Moore Machine
5.4.1 Moore Machine Described Using Three Processes
5.4.2 Moore Machine Described with Two Processes
5.5 VHDL Implementation for Mealy Machine
5.6 Examples: States Machines in VHDL
5.6.1 4-Bit BCD Counter FSM
5.6.2 Sequence Detector FSM
5.6.3 Parity Checker
5.7 Summary
Part III Laboratory Projects
6 Digital Projects Carried Out on the FPGA Platform
6.1 Introduction
6.2 Lab #1 Simple Calculator Design
6.2.1 Design of Arithmetic and Logic Unit (ALU)
6.2.2 Design of Multiplexers and Demultiplexers
6.2.3 Design of Registers
6.2.4 Design of Controller
6.2.5 Implementation of the Final Design of the Mini-calculator on the FPGA Platform
6.3 Lab #2 Digital Clock
6.3.1 Design of Digital Clock
6.3.2 Design of Frequency Divider
6.3.3 Design of Counters
6.3.4 Design of 7-Segment Display
6.3.5 Final Design of Digital Clock
6.3.6 Implementation of the Final Design of Digital Clock on the FPGA Platform
6.4 Lab #3 Design of Traffic Light Controller
6.4.1 Traffic Light Controller Operation
6.4.2 Design Traffic Light Controller in VHDL
6.4.3 Traffic Light Controller Implementation in the FPGA Platform
6.5 Lab #4 Vending Machine Controller
6.5.1 State Machine Diagram of Vending Machine
6.5.2 VHDL Implementation and Simulation of Vending Machine
6.5.3 Implementation and Validation on FPGA Platform
6.6 Lab #5 Control of a 4-Phase Step Motor (Speed and Position)
6.6.1 Laboratory Design Specifications
6.6.2 Stepper Motor Control: Speed and Position
6.7 Summary
Part IV FPGA Applications
7 FPGA Applications in Renewable Energy Systems: Photovoltaic, Wind-Turbine and Hybrid Systems
7.1 Introduction
7.2 Neural Networks
7.3 Case Studies
7.3.1 Case Study 1: FPGA-Based Intelligent Photovoltaic Module Simulator
7.3.2 Case Study 2: FPGA-Based Implementation of Irradiance Equalization Algorithm for Reconfigurable Photovoltaic
7.3.3 Case Study 3: FPGA-Based Implementation of an MPPT Algorithm
7.3.4 Case Study 5: XSG-Based Implementation Control of Grid-Connected Hybrid System (PV-WT)
7.4 Summary
References
Appendix A VHDL Codes of MLP Modules
Appendix B VHDL Codes of the Interconnection Reconfiguration Algorithm Between the PV Panels
Appendix C P & O Algorithm
References