VLSI Design: a Practical Guide for FPGA and ASIC Implementations

✍ Scribed by Chandrasetty, Vikram Arkalgud

• Publisher: Springer Science+Business Media, LLC
• Year: 2011
• Tongue: English
• Leaves: 119
• Series: SpringerBriefs in Electrical and Computer Engineering
• Edition: 1
• Category: Library

✦ Synopsis

This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphics, Synopsys and Cadence.

✦ Table of Contents

4.1.2.3 Design Calculations......Page 3
4.1.2.6 Simulations and Verification......Page 7
BPSK Demodulator Design......Page 9
4.2.2 Layout Design......Page 11
Cover......Page 1
4.1.2.1 Specifications......Page 2
VLSI Design......Page 4
3.2.1 Introduction......Page 5
Preface......Page 8
Contents......Page 10
Abbreviations......Page 12
2.2.4 Simulation and Synthesis Results......Page 15
4.1.2.4 Design Calculation Results......Page 6
3.3.2 Physical Design Flow......Page 13
3.3.2.2 Floor Planning......Page 14
1.1.1 Plan of SRAM Cell and Array......Page 16
1.1.2 Design of 6 Transistor SRAM Cell......Page 17
1.1.4 Layout of SRAM Cell......Page 18
1.1.5 Design of SRAM Array......Page 19
1.2.1.2 Sense Amplifier......Page 20
1.2.1.3 Pre-Charge Circuit......Page 22
2.4.3 Simulation and Synthesis Results......Page 24
Appendix......Page 26
References......Page 30
1.2.3 Simulations of Complete SRAM Chip......Page 25
3.3.2.8 Design for Manufacturability......Page 29
2.1.1.1 Overview of PN Sequence Generator......Page 32
Design......Page 33
2.1.2.1 Overview of DS-SS Transmitter System......Page 35
1.2.1.4 Data I/O Control Logic......Page 23
Appendix......Page 27
Chapter 2: FPGA Application Design......Page 31
Block Diagram......Page 34
Oscillator Design......Page 36
BPSK Modulator Design......Page 37
2.1.2.3 Simulation Results for DS-SS Transmitter......Page 38
BPSK Demodulator Design......Page 39
Low Pass Filter and Decision Device Design......Page 40
2.1.3.3 Noise Models and Synchronization......Page 41
2.1.3.4 Simulation Results for DS-SS Receiver......Page 42
2.2.1 Concepts of FIR Filter......Page 43
2.2.2 Low Pass FIR Filter Design......Page 44
2.2.3 Distributed Arithmetic Architecture......Page 45
2.3.1 Concepts of DCT......Page 46
2.3.2 DCT Architectures on FPGA......Page 47
2.3.3 Scaled 1-D 8-Point DCT Architecture......Page 48
2.3.4 Simulation and Synthesis Results......Page 49
2.4.1 Concepts of Convolution Codes......Page 50
2.4.2 Viterbi Decoder......Page 52
2.4.3 Simulation and Synthesis Results......Page 54
Appendix......Page 56
References......Page 60
3.1.1 Introduction......Page 61
3.1.3 Implementation and Simulations......Page 62
3.1.4 Results Analysis and Conclusion......Page 63
3.2.1 Introduction......Page 65
3.2.3 Matrix Multiplier Design......Page 66
3.2.5 Analysis of Results and Conclusion......Page 68
3.3.1 Introduction to Systolic Array Matrix Multiplier......Page 71
3.3.2 Physical Design Flow......Page 73
3.3.2.1 Design Setup......Page 74
3.3.2.3 Power Planning......Page 76
3.3.2.4 Timing Setup......Page 77
3.3.2.5 Placement......Page 80
3.3.2.6 Clock Tree Synthesis......Page 82
3.3.2.7 Routing......Page 85
3.3.2.8 Design for Manufacturability......Page 89
3.3.3 Results and Conclusion......Page 92
Appendix......Page 93
References......Page 95
4.1.1 Introduction......Page 96
4.1.2.1 Specifications......Page 97
4.1.2.2 Schematic of OPAMP......Page 98
4.1.2.4 Design Calculation Results......Page 101
4.1.2.6 Simulations and Verification......Page 102
4.2.2 Layout Design......Page 106
4.2.2.2 Layout Design of OPAMP......Page 107
4.2.3 Summary and Results......Page 111
Appendix......Page 112
References......Page 117
About the Author......Page 118