This paper uses a CAD methodology proposed by the authors to design a low-power second-order M. This modulator has been fabricated in a 0•7 m CMOS technology to be used as the front-end of an energy-metering mixed-signal ASIC and features 16•4 bit at a digital output rate of 9•6 kHz with a power con
Poles and zeros of bandpass filters for high-performance sigma-delta modulators
✍ Scribed by M. Bellanger; A. Vouillemont; S. Azrouf; F. Gourgue
- Publisher
- John Wiley and Sons
- Year
- 1995
- Tongue
- English
- Weight
- 554 KB
- Volume
- 23
- Category
- Article
- ISSN
- 0098-9886
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✦ Synopsis
SUIbf MARY
High-performance bandpass sigma-delta modulators find applications in digital mobile radio for accurate analogue-todigital conversion in receivers.
An approach based on the positioning of the poles and zeros is proposed for the digital design of the high-order loop filters which are required. Inverse notch filter sections are cascaded in a first step and then poles and zeros are moved to meet the performance objectives and achieve system stability.
A distinct feature of the analysis and design technique presented is that it takes stability into account explicitly.
Examples illustrate the practicality of the method as well LS the level of performance which can be achieved in theory. The integrated circuit realization still has to be investigated to confirm the potential of the proposed design approach.
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