✦ LIBER ✦

Performance evaluation of delay testable enhanced scan flip-flop

✍ Scribed by Ashok Kumar Suhag, Vivek Shrivastava

Book ID: 118302210
Publisher: Springer-Verlag
Year: 2012
Tongue: English
Weight: 250 KB
Volume: 3
Category: Article
ISSN: 0975-6809
DOI: 10.1007/s13198-012-0124-7

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Construction of SEU Tolerant Flip-Flops

Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing

✍ Namba, K.; Ikeda, T.; Ito, H. 📂 Article 📅 2010 🏛 IEEE 🌐 English ⚖ 611 KB

Flip–flop selection for partial enhance

Flip–flop selection for partial enhance scan chain using DTESFF for high transition delay fault coverage

✍ Ashok Kumar Suhag, Vivek Shrivastava… 📂 Article 📅 2013 🏛 Springer-Verlag 🌐 English ⚖ 404 KB

Evaluation of delay fault testability of

Evaluation of delay fault testability of LUTs for the enhancement of application-dependent testing of FPGAs

✍ Andrzej Krasniewski 📂 Article 📅 2003 🏛 Elsevier Science 🌐 English ⚖ 340 KB

[ACM ISLPED'01: Proceedings of the 2001

[ACM ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design - Huntington Beach, CA, USA (6-7 Aug. 2001)] ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581) - Comparative delay and energy of single edge-triggered and dual edge-triggered pulsed flip-flops for high-performance microprocessors

✍ Tschanz, J.; Narendra, S.; Zhanping Chen, ; Borkar, S.; Sachdev, M.; Vivek De, 📂 Article 📅 2001 🏛 ACM 🌐 English ⚖ 522 KB

Sponsored By Acm/sigda And Ieee Circuits And Systems Society ; With Technical Co-sponsorship From The Ieee Solid-state Circuits Society And The Ieee Electron Devices Society. Acm Order Number 477014--t.p. Verso. Ieee Catalog No. 01th8581--t.p. Verso. Includes Bibliographical References And Author In