𝔖 Bobbio Scriptorium
✦   LIBER   ✦

Performance evaluation and cost analysis of cache protocol extensions for shared-memory multiprocessors

✍ Scribed by Dahlgren, F.; Dubois, M.; Stenstrom, P.


Book ID
119772887
Publisher
IEEE
Year
1998
Tongue
English
Weight
575 KB
Volume
47
Category
Article
ISSN
0018-9340

No coin nor oath required. For personal study only.


πŸ“œ SIMILAR VOLUMES


Chip size and performance evaluations of
✍ Takahiro Sasaki; Tomohiro Inoue; Nobuhiko Omori; Tetsuo Hironaka; Hans J. Mattau πŸ“‚ Article πŸ“… 2005 πŸ› John Wiley and Sons 🌐 English βš– 377 KB

## Abstract Recent semiconductor technology has made on‐chip multiprocessors with several CPUs and cache memories on a single chip a realistic possibility. Generally, conventional multiprocessor systems with shared memory offer a simple programming model, but need a cache coherency mechanism that m