PCI Express Card Electromechanical Specification, Revision 2.0

• Publisher: PCI-SIG
• Year: 2007
• Tongue: English
• Leaves: 106
• Category: Library

✦ Table of Contents

Contents
1. Introduction
1.1. Terms and Definitions
1.2. Reference Documents
1.3. Specification Contents
1.4. Objectives
1.5. Electrical Overview
1.6. Mechanical Overview
2. Auxiliary Signals
2.1. Reference Clock
2.1.1. Low Voltage Swing, Differential Clocks
2.1.2. Spread Spectrum Clocking (SSC)
2.1.3. REFCLK AC Specifications
2.1.4. REFCLK Phase Jitter Specification For 2.5 GT/s Signaling Support
2.1.5. REFCLK Phase Jitter Specification For 5 GT/s Signaling Support
2.2. PERST# Signal
2.2.1. Initial Power-Up (G3 to S0)
2.2.2. Power Management States (S0 to S3/S4 to S0)
2.2.3. Power Down
2.3. WAKE# Signal
2.4. SMBus (Optional)
2.4.1. Capacitive Load of High-power SMBus Lines
2.4.2. Minimum Current Sinking Requirements for SMBus Devices
2.4.3. SMBus “Back Powering” Considerations
2.4.4. Power-on Reset
2.5. JTAG Pins (Optional)
2.6. Auxiliary Signal Parametric Specifications
2.6.1. DC Specifications
2.6.2. AC Specifications
3. Hot Insertion and Removal
3.1. Scope
3.2. Presence Detect
4. Electrical Requirements
4.1. Power Supply Requirements
4.2. Power Consumption
4.3. Power Supply Sequencing
4.4. Power Supply Decoupling
4.5. Electrical Topologies and Link Definitions
4.5.1. Topologies
4.5.2. Link Definition
4.6. Electrical Budgets
4.6.1. AC Coupling Capacitors
4.6.2. Insertion Loss Values (Voltage Transfer Function)
4.6.3. Jitter Values
4.6.4. Crosstalk
4.6.5. Lane-to-Lane Skew
4.6.6. Equalization
4.6.7. Skew within the Differential Pair
4.6.8. Differential Data Trace Impedance
4.6.9. Differential Data Trace Propagation Delay
4.7. Eye Diagrams at the Add-in Card Interface
4.7.1. Add-in Card Transmitter Path Compliance Eye Diagram at 2.5 GT/s
4.7.2. Add-in Card Transmitter Path Compliance Eye Diagrams at 5 GT/s
4.7.3. Add-in Card Minimum Receiver Path Sensitivity Requirements at 2.5 GT/s
4.7.4. Add-in Card Minimum Receiver Path Sensitivity Requirements at 5 GT/s
4.7.5. System Board Transmitter Path Compliance Eye Diagram at 2.5 GT/s
4.7.6. System Board Transmitter Path Compliance Eye Diagram at 5 GT/s
4.7.7. System Board Minimum Receiver Path Sensitivity Requirements at 2.5 GT/s
4.7.8. System Board Minimum Receiver Path Sensitivity Requirements at 5 GT/s
5. Connector Specification
5.1. Connector Pinout
5.2. Connector Interface Definitions
5.3. Signal Integrity Requirements and Test Procedures
5.3.1. Signal Integrity Requirements
5.3.2. Signal Integrity Requirements and Test Procedures for 2.5 GT/s Support
5.3.3. Signal Integrity Requirements and Test Procedures for 5 GT/s Support
5.3.3.1 Test Fixture Requirements
5.4. Connector Environmental and Other Requirements
5.4.1. Environmental Requirements
5.4.2. Mechanical Requirements
5.4.3. Current Rating Requirement
5.4.4. Additional Considerations
6. Add-in Card Form Factors and Implementation
6.1. Add-in Card Form Factors
6.2. Connector and Add-in Card Locations
6.3. Card Interoperability
A. Insertion Loss Values (Voltage Transfer Function) (Informational Only)
Acknowledgements