Partial Scan Testing on the Register-Transfer Level

Testing power-analysis attack susceptibi

Testing power-analysis attack susceptibility in register-transfer level designs

✍ Bucci, M.; Luzzi, R.; Menichelli, F.; Menicocci, R.; Olivieri, M.; Trifiletti, A 📂 Article 📅 2007 🏛 The Institution of Engineering and Technology 🌐 English ⚖ 100 KB

Efficient board interconnect testing usi

Efficient board interconnect testing using the split boundary scan register

✍ Nazar S. Haider; Nick Kanopoulos 📂 Article 📅 1993 🏛 Springer US 🌐 English ⚖ 688 KB

Register-transfer-level power estimation

Register-transfer-level power estimation based on technology decomposition

✍ Chen, C.; Ahmadi, M. 📂 Article 📅 2003 🏛 The Institution of Electrical Engineers 🌐 English ⚖ 257 KB

A test evaluation technique for VLSI cir

A test evaluation technique for VLSI circuits using register-transfer level fault modeling

✍ Thaker, P.A.; Agrawal, V.D.; Zaghloul, M.E. 📂 Article 📅 2003 🏛 IEEE 🌐 English ⚖ 526 KB

Modelling of digital circuits function a

Modelling of digital circuits function and functional faults on register transfer level

✍ Jacek Gawin 📂 Article 📅 1992 🏛 Elsevier Science ⚖ 245 KB

Register transfer level power optimizati

Register transfer level power optimization with emphasis on glitch analysis and reduction

✍ Raghunathan, A.; Dey, S.; Jha, N.K. 📂 Article 📅 1999 🏛 IEEE 🌐 English ⚖ 336 KB