A test evaluation technique for VLSI circuits using register-transfer level fault modeling

✍ Scribed by Thaker, P.A.; Agrawal, V.D.; Zaghloul, M.E.

• Book ID: 118698419
• Publisher: IEEE
• Year: 2003
• Tongue: English
• Weight: 526 KB
• Volume: 22
• Category: Article
• ISSN: 0278-0070
• DOI: 10.1109/tcad.2003.814958