✦ LIBER ✦
A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models
✍ Scribed by Fujiwara, H.; Iwata, H.; Yoneda, T.; Chia Yee Ooi
- Book ID
- 117908169
- Publisher
- IEEE
- Year
- 2008
- Tongue
- English
- Weight
- 990 KB
- Volume
- 27
- Category
- Article
- ISSN
- 0278-0070
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