Design of a WSI scale parallel processor
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Yoshichika Fujioka; Nobuhiro Tomabechi
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Article
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2000
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John Wiley and Sons
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English
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A restructurable (reconfigurable) parallel VLSI processor designed to minimize the operation delay time which can be generally used for various operations necessary for controlling an intelligent robot was proposed previously by the authors. This processor is constructed by connecting a number of pr