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Parallel pipelined histogram architectures

โœ Scribed by Cadenas, J.; Sherratt, R.S.; Huerta, P.


Book ID
111917419
Publisher
The Institution of Electrical Engineers
Year
2011
Tongue
English
Weight
154 KB
Volume
47
Category
Article
ISSN
0013-5194

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Parallelization of WHILE loops on pipeli
โœ Parthasarathy P. Tirumalai; Meng Lee; Michael S. Schlansker ๐Ÿ“‚ Article ๐Ÿ“… 1991 ๐Ÿ› Springer US ๐ŸŒ English โš– 977 KB

Modulo scheduling theory can be applied successfully to overlap Fortran DO loops on pipelined computers issuing multiple operations per cycle both with and without special loop architectural support. This paper shows that a broader class of loops--REPEAT-UNTIL, WHILE, and loops with more than one ex