Parallel digital neural hardware for controller design
✍ Scribed by S. Neusser; B. Höfflinger
- Publisher
- Elsevier Science
- Year
- 1996
- Tongue
- English
- Weight
- 725 KB
- Volume
- 41
- Category
- Article
- ISSN
- 0378-4754
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✦ Synopsis
A general comparison with regard to speed and size of digital neural hardware on different levels of parallelism results in the design of a fully parallel architecture based on a bit-serial neural hardware model with a new quadratic squashing function. This nonlinear squashing function is well suited for small parallel digital hardware implementations. A cascadable semicustom chip containing six neurons was designed based on this model. This neurochip is used in the hardware implementation of a neurocontroller. The controller is developed for the lateral control of a vehicle and trained from only 6000 samples of human driving behavior recorded on a German federal highway.
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