A general comparison with regard to speed and size of digital neural hardware on different levels of parallelism results in the design of a fully parallel architecture based on a bit-serial neural hardware model with a new quadratic squashing function. This nonlinear squashing function is well suite
A design environment for digital hardware
β Scribed by PW Foulk; RA Mason
- Publisher
- Elsevier Science
- Year
- 1980
- Tongue
- English
- Weight
- 124 KB
- Volume
- 12
- Category
- Article
- ISSN
- 0010-4485
No coin nor oath required. For personal study only.
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