Optimisation of on-chip design-for-test infrastructure for maximal multi-site test throughput

✍ Scribed by Goel, S.K.; Marinissen, E.J.

• Book ID: 114448675
• Publisher: The Institution of Electrical Engineers
• Year: 2005
• Tongue: English
• Weight: 645 KB
• Volume: 152
• Category: Article
• ISSN: 1350-2387
• DOI: 10.1049/ip-cdt:20050046