๐”– Bobbio Scriptorium
โœฆ   LIBER   โœฆ

Optimal matrix multiplication on fault-tolerant VLSI arrays

โœ Scribed by Varman, P.J.; Ramakrishnan, I.V.

Book ID
119771855
Publisher
IEEE
Year
1989
Tongue
English
Weight
701 KB
Volume
38
Category
Article
ISSN
0018-9340

No coin nor oath required. For personal study only.

๐Ÿ“œ SIMILAR VOLUMES

VLSI systolic arrays for band matrix mul
VLSI systolic arrays for band matrix multiplication
โœ G. Alia ๐Ÿ“‚ Article ๐Ÿ“… 1983 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 771 KB

The advent of VLSI technology has deeply modified the design of digital systems. The structure of special algorithms is now close to the structure of communication and computing resources on the silicon chip. Modular and regular structures allow parallel VLSI algorithms with good figures of complexi

Mapping matrix multiplication algorithm
Mapping matrix multiplication algorithm onto fault-tolerant systolic array
โœ N.M. Stojanoviฤ‡; E.I. Milovanoviฤ‡; I. Stojmenoviฤ‡; T.. Milovanoviฤ‡; T.I. Tokiฤ‡ ๐Ÿ“‚ Article ๐Ÿ“… 2004 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 891 KB

An approach to design fault-tolerant hexagonal systolic array (SA) for multiplication of rectangular matrices is described. The approach comprises three steps. First, redundancies are introduced at the computational level by deriving three equivalent algorithms but with disjoint index spaces. Second