<p>This book provides various design techniques for switched-capacitor on-chip high-voltage generators, including charge pump circuits, regulators, level shifters, references, and oscillators. Readers will see these techniques applied to system design in order to address the challenge of how the on-
On-chip High-Voltage Generator Design: Design Methodology for Charge Pumps
โ Scribed by Toru Tanzawa (auth.)
- Publisher
- Springer International Publishing
- Year
- 2016
- Tongue
- English
- Leaves
- 271
- Series
- Analog Circuits and Signal Processing
- Edition
- 2
- Category
- Library
No coin nor oath required. For personal study only.
โฆ Synopsis
This book provides various design techniques for switched-capacitor on-chip high-voltage generators, including charge pump circuits, regulators, level shifters, references, and oscillators. Readers will see these techniques applied to system design in order to address the challenge of how the on-chip high-voltage generator is designed for Flash memories, LCD drivers, and other semiconductor devices to optimize the entire circuit area and power efficiency with a low voltage supply, while minimizing the cost. This new edition includes a variety of useful updates, including coverage of power efficiency and comprehensive optimization methodologies for DC-DC voltage multipliers, modeling of extremely low voltage Dickson charge pumps, and modeling and optimum design of AC-DC switched-capacitor multipliers for energy harvesting and power transfer for RFID.
โฆ Table of Contents
Front Matter....Pages i-xix
System Overview and Key Design Considerations....Pages 1-15
Basics of Charge Pump Circuit....Pages 17-66
Design of DC-DC Dickson Charge Pump....Pages 67-122
Design of ACโDC Charge Pump....Pages 123-156
Charge Pump State of the Art....Pages 157-175
Pump Control Circuits....Pages 177-219
System Design....Pages 221-250
Back Matter....Pages 251-254
โฆ Subjects
Circuits and Systems; Electronic Circuits and Devices; Electronics and Microelectronics, Instrumentation
๐ SIMILAR VOLUMES
Reuse Methodology Manual for System-on-a-Chip Designs, Third Edition outlines a set of best practices for creating reusable designs for use in an SoC design methodology. These practices are based on the authors' experience in developing reusable designs, as well as the experience of design teams in
<p>Silicon technology now allows us to build chips consisting of tens of millions of transistors. This technology not only promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendor
<p><P><EM>"Tools alone aren't enough to reduce dynamic and leakage power in complex chip designs - a well-planned methodology is needed. Following in the footsteps of the successful Reuse Methodology Manual (RMM), authors from ARM and Synopsys have written this Low Power Methodology Manual (LPMM) to