Noise Contamination in Nanoscale VLSI Circuits

✍ Scribed by Selahattin Sayil

• Publisher: Springer
• Year: 2022
• Tongue: English
• Leaves: 142
• Series: Synthesis Lectures on Digital Circuits & Systems
• Category: Library

✦ Synopsis

This textbook provides readers with a comprehensive introduction to various noise sources that significantly reduce performance and reliability in nanometer-scale integrated circuits. The author covers different types of noise, such as crosstalk noise caused by signal switching of adjacent wires, power supply noise or IR voltage drop in the power line due to simultaneous buffer / gate switching events, substrate coupling noise, radiation-induced transients, thermally induced noise and noise due to process and environmental Coverages also includes the relationship between some of these noise sources, as well as compound effects, and modeling and mitigation of noise mechanisms.

✦ Table of Contents

Preface
Contents
About the Author
1 Introduction
References
2 Interconnect Noise
2.1 Introduction
2.2 Miller Factor Analysis
2.2.1 Miller Factor Estimation Under Exponential Waveforms
2.2.2 The Simulation Results
2.2.3 Summary
2.3 Interconnect Models
2.4 Elmore Delay Formulation
2.5 Crosstalk Mitigation Techniques
2.5.1 Driver Sizing
2.5.2 Wire Spacing
2.5.3 Wire Sizing
2.5.4 Power Supply Shielding
2.5.5 Buffer Insertion Method
2.5.6 A New Methodology for Crosstalk Reduction Using Transmission Gates
References
3 Modeling and Prediction of Crosstalk Noise
3.1 Introduction
3.2 The 4-π Model
3.3 Passive Aggressor Modeling
3.4 RC Trees and Branch Modeling
3.5 Aggressor Waveform Calculation at Coupling Node
3.6 Output Voltage Formulation
3.7 Validation of the Proposed Model
3.8 Multiple Active Aggressors
3.9 Conclusion
References
4 Clock Uncertainty and Power Supply Noise
4.1 Clock Skew and Jitter
4.2 Sources of Skew and Jitter
4.3 Clock Distribution
4.4 Thermal Impact on Clock Skew
4.5 Power Supply Noise
References
5 Substrate Noise
5.1 Substrate Noise Mechanisms
5.2 Minimization of Substrate Noise
References
6 Single Event Soft Errors
6.1 Introduction
6.2 Circuit Level Modeling of Single Event Strikes
6.3 Mitigation of Single Event Soft Errors
6.4 Soft Error Mechanisms
6.5 Single Event Crosstalk Noise Prediction/Modeling
References
7 Thermal Noise
7.1 Introduction
7.2 Compensation of Thermally Induced Clock Skew
7.3 Thermally Induced Soft Errors
7.4 Analysis and Mitigation of Thermally Induced Single Event Crosstalk
References
8 PVT Variations
8.1 Introduction
References
Index