## Abstract A low phase‐noise frequency synthesizer design for ultrawideband is demonstrated in a 0.18‐μm CMOS process. It combines a low phase‐noise voltage‐controlled oscillator with two‐stage dividers and a switched buffer multiplexer with low layout complexity. Because of the symmetrical indepe
✦ LIBER ✦
New method to design a low-phase-noise millimeter-wave PLL frequency synthesizer
✍ Scribed by Haihong Ma; Xiaohong Tang; Tao Wu; Zhou Cao
- Publisher
- John Wiley and Sons
- Year
- 2006
- Tongue
- English
- Weight
- 143 KB
- Volume
- 48
- Category
- Article
- ISSN
- 0895-2477
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✦ Synopsis
Abstract
Based on the theory of phase‐noise analysis and estimation, a new method to obtain low‐phase‐noise millimeter‐wave phase‐locked loop (PLL) frequency synthesizer is presented. In order to verify its feasibility, a W‐band PLL frequency synthesizer working at 95 GHz is designed. A low phase noise of −90.44 dBc/Hz at 10‐kHz offset is achieved, which is well coincident with the estimated value. © 2006 Wiley Periodicals, Inc. Microwave Opt Technol Lett 48: 1194–1197, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21583
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