✦ LIBER ✦

Multiple-path execution for chip multiprocessors

✍ Scribed by Matthew C. Chidester; Alan D. George; Matthew A. Radlinski

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Nahalal: Cache Organization for Chip Mul

✍ Guz, Z.; Keidar, I.; Kolodny, A.; Weiser, U.C. 📂 Article 📅 2007 🏛 IEEE 🌐 English ⚖ 178 KB

Transient-fault recovery for chip multip

✍ Gomaa, M.A.; Scarbrough, C.; Vijaykumar, T.N.; Pomeranz, I. 📂 Article 📅 2003 🏛 IEEE 🌐 English ⚖ 346 KB

ReMAP: A Reconfigurable Architecture for

✍ Watkins, M.A.; Albonesi, D.H. 📂 Article 📅 2011 🏛 IEEE 🌐 English ⚖ 898 KB

Load Balancing for Parallel Query Execut

✍ Luc Bouganim; Daniela Florescu; Patrick Valduriez 📂 Article 📅 1999 🏛 Springer US 🌐 English ⚖ 159 KB

On-chip memory space partitioning for ch

✍ Ozturk, O.; Kandemir, M.; Irwin, M.J. 📂 Article 📅 2010 🏛 The Institution of Engineering and Technology 🌐 English ⚖ 917 KB

Enhancing multiple-path speculative exec

✍ Jenn-Yuan Tsai; Pen-Chung Yew 📂 Article 📅 1999 🏛 Elsevier Science 🌐 English ⚖ 353 KB