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Multilevel logic synthesis technique for efficient verification testing

โœ Scribed by Lee, Y.-H.; Chong, J.W.; Russell, G.

Book ID
114448284
Publisher
The Institution of Electrical Engineers
Year
1997
Tongue
English
Weight
920 KB
Volume
144
Category
Article
ISSN
1350-2387

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Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic
โœ Bryant, Randal E.; German, Steven; Velev, Miroslav N. ๐Ÿ“‚ Article ๐Ÿ“… 2001 ๐Ÿ› Association for Computing Machinery ๐ŸŒ English โš– 312 KB

The logic of Equality with Uninterpreted Functions (EUF) provides a means of abstracting the manipulation of data by a processor when verifying the correctness of its control logic. By reducing formulas in this logic to propositional formulas, we can apply Boolean methods such as ordered Binary Deci