Scaling solid-state devices has the peculiar property of improving cost, performance, and power, which has historically given any company with the latest technology a large competitive advantage in the market. As a result, the microelectronics industry has driven transistor feature size scaling from 10 Β΅m to ~30 nm 4-6 during the past 40 years. During most of this time, scaling simply consisted of reducing the feature size. However, during certain periods, there were major changes as with the industry move from Si bipolar to p-channel metal-oxidesemiconductor (MOS), then to n-channel MOS, and finally to complementary MOS (CMOS) planar transistors in the 1980s, which has remained the dominate technology for the past two decades. The big challenge going forward is that the end of planar CMOS transistor scaling is near as the transistor size approaches tens of nanometers. How the industry evolves after this limit is reached is unclear.
To address these challenges, present day research is focused on identifying new materials and devices that can augment and/or potentially replace the aging ~50-year-old Si transistor 7 . Two approaches under investigation are: (1) nonclassical CMOS, which consists of new channel materials and/or multigate fully depleted device structures; and (2) alternatives to CMOS, such as spintronics, single electron devices, and molecular computing 8,9 . While some of these non-Si research areas are important and will be successful in new applications and markets 10 , it seems unlikely any of the non-Si options can replace the Si transistor for the $300 billion microelectronics industry in the foreseeable future (perhaps as long as 30 years). This review aims to explain the future of Si microelectronics, key issues at the end of the Si roadmap, and the time frame for possible non-Si technology replacements. We first discuss the state of Moore's law and conventional planar Si transistor scaling limits. Next, we cover the issues at the end of the Si roadmap based on current technology trends. We end, perhaps foolhardily, with an assessment of nonclassical CMOS and alternatives to CMOS. The key takeaway messages are that simple scaling has ended, there is enormous life left in planar Si CMOS technology, and nothing is on the horizon to replace it for mainstream logic applications.
Soon after Bardeen, Brattain, and Shockley invented a solid-state device in 1947 1 to replace electron vacuum tubes, the microelectronics industry and a revolution started. Since its birth, the industry has experienced four decades of unprecedented explosive growth driven by two factors: Noyce and Kilby inventing the planar integrated circuit 2,3 and the advantageous characteristics that result from scaling (shrinking) solid-state devices.