Microprocessor Architectures and Systems. RISC, CISC and DSP

✍ Scribed by Steve Heath (Auth.)

• Publisher: Elsevier Ltd, Butterworth-Heinemann
• Year: 1991
• Tongue: English
• Leaves: 294
• Category: Library

✦ Synopsis

Intended for both engineers and managers who are given the task of selecting an architecture or design approach, this book examines the developments of Motorola's CISC, RISC and DSP processors. It describes the typical system configurations and engineering trade-offs that are made. The text provides a primer and history of the three basic microprocessor architectures and describes the ways in which the architectures react with the system and covers memory designs, memory management and cache memories. It examines interrupt and exception handling, the effect on real-time applications, basic multiprocessing ideas, shows how certain characteristics can be exploited, looks at semiconductor technology, the changing design cycle and its implications for the design process and commercial success and future processor generations describing the criteria that should be examined when selecting a processor

✦ Table of Contents

Content:
Front Matter, Page iii
Copyright, Page iv
Dedication, Page v
Preface, Pages xi-xii
Acknowledgements, Page xiii
1 - Complex instruction set computers, Pages 1-43
2 - 32-bit CISC processors, Pages 44-71
3 - The RISC challenge, Pages 72-97
4 - Digital signal processing, Pages 98-118
5 - Memory, memory management and caches, Pages 119-153
6 - Real-time software, interrupts and exceptions, Pages 154-174
7 - Multiprocessing, Pages 175-188
8 - Application ideas, Pages 189-212
9 - Semiconductor technology, Pages 213-223
10 - The changing design cycle, Pages 224-236
11 - The next generations, Pages 237-258
12 - Selecting a microprocessor architecture, Pages 259-266
Appendix A - Benchmarking: ‘lies, damn lies and benchmarks’ (with apologies to Benjamin Disraeli), Pages 267-272
Appendix B - Binary compatibility standards, Pages 273-279
Index, Pages 280-288