Preface
Introduction
Contents
Chapter 1: Means to Accelerate Transfer of Information Between Integrated Circuits
1.1 General Issues of Means to Accelerate Transfer of Information Between Integrated Circuits
1.1.1 Importance of Means to Accelerate Transfer of Information Between Integrated Circuits
1.1.2 Current State and Issues of Existing Means of Increasing the Speed of Receiving Sequential Information in an Integrated ...
1.1.3 Proposed Approaches to Increase the Speed of Receiving Sequential Information in an Integrated Circuit
1.2 Methods to Increase the Speed of Receiving Sequential Information in an Integrated Circuit
1.2.1 Method to Increase the Speed of Receiving Sequential Information with the Use of a Circuit with Negative Capacitance in ...
1.2.2 Method to Increase the Speed of Receiving Sequential Information with the Use of a High-Speed Comparator with Low Input ...
1.2.3 Method to Increase the Speed of Receiving Sequential Information Due to Processing of the Signal Transmitted by Pulse Am...
References
Chapter 2: Design Methods of Integrated Circuits, Working Under Non-standard Operating Conditions
2.1 General Issues of Design Methods of Integrated Circuits, Working Under Non-standard Operating Conditions
2.1.1 Need for Design Methods of Integrated Circuits, Working Under Non-standard Operating Conditions
2.1.2 Existing Design Methods of Integrated Circuits, Working Under Non-standard Operating Conditions
The Method of Reducing Offset in Comparators
The Method of Offset Reduction Using a Digital Control Circuit in Receivers of Integrated Circuits
A Method of Continuously Receiving Sequential Data Using Digital Delay Lines
2.1.3 Existing Problems of Design Methods of Integrated Circuits, Working Under Non-standard Operating Conditions
Existing Problems of Offset Reduction Method in Comparators
The Existing Problems in Offset Cancellation Method Based on Digital Calibration Circuit, for Input Stage of a Receiver
Existing Problems in the Method of Continuous Reception of Sequential Data Using Digital Delay Lines
2.1.4 Principles of Increasing the Stability of Integrated Circuits, Working Under Non-standard Operating Conditions
2.2 Reduction of Offset Value Caused by aging Phenomena Through Adding Transmission Gates and Transistor Switches in Comparato...
2.3 Incorporation of the Current DAC in the Method of Offset Reduction Through the Circuit with Digital Control of IC Receiver
2.4 Implementation of Negative Feedback in DDLs
2.4.1 Conclusions
2.5 Design Methods of Integrated Circuits, Working Under Non-standard Operating Conditions
2.5.1 Method of Reducing Offset, Caused by Aging Phenomena in Comparators
2.5.2 Method of Reducing the Offset Caused by Sharp Fluctuations in Ambient Temperature in the Receiver
2.5.3 Method of Reducing the Offset Caused by Sharp Voltage and Temperature Fluctuations in Digital Delay Lines
2.6 Conclusions
References
Chapter 3: Signal Transmission Calibration Systems in Integrated Circuits
3.1 General Issues of Signal Transmission Calibration Systems in Integrated Circuits
3.1.1 Importance of Signal Transmission Calibration Means in Integrated Circuits
3.1.2 Importance of Developing Signal Transmission Calibration Means in Integrated Circuits
Problems of Developing Signal Transmission Calibration Means in Integrated Circuits and Their Measurements
3.1.3 Current State and Issues of Design Methods of Signal Transmission Calibration Systems in Integrated Circuits
Signal Reading Problems Caused by Wave Reflections at the Receiver
Problems Caused by Data Distortions at the Transmitter Sub-node
Problems Caused by PVT Deviations in Transmitter Sub-nodes
Signal Transmission Calibration Problems Caused by Transmission Lines
Design Principles of Signal Transmission Calibration Systems in Integrated Circuits
3.2 Design Principles of Signal Transmission Calibration Systems in Integrated Circuits
3.2.1 Method of Detection and Self-Regulation of Duty Cycle Deviations in High-Speed Integrated Circuits
Estimation of Duty Cycle Deviation Detection and Efficiency of Self-Calibration Method
3.2.2 Method of Increasing the Reliability of High-frequency Data in Transmitters
Evaluation of Effectiveness of the Method of Increasing the Reliability of High-frequency Data in Transmitter Sub-nodes
3.2.3 Method of Calibration of Asymmetries of Rise/Fall Times of High-frequency Signals
Evaluation of Effectiveness of Calibration Method of Asymmetries of Rise/Fall Times of High-frequency Signals
3.2.4 Calibration Method of Signal Distortion Caused by Transmission Line
Evaluation of Effectiveness of Calibration Method of Signal Distortion Caused by Transmission Line
References
Chapter 4: Methods to Improve Linearity of Signal´s Analog-to-Digital Conversion with Self-Calibration
4.1 General Issues to Improve Linearity of Signal´s Analog-to-Digital Conversion with Self-Calibration
4.1.1 Importance of Means to Improve the Linearity of Signal´s Analog-to-Digital Conversion with Self-Calibration
4.1.2 Need for Means to Improve the Linearity of Signal´s Analog-to-Digital Conversion with Self-Calibration
4.1.3 Causes of Nonlinearity Occurrence in Signal´s Analog-to-Digital Conversion and the Importance and Necessity of its Reduc...
4.1.4 Causes of Nonlinearity Occurrence Signal´s in Analog-to-Digital Conversion and the Importance and Necessity of its Reduc...
4.1.5 Causes of Nonlinearity Occurrence in Signal´s Analog-to-Digital Conversion and the Importance and Necessity of Its Reduc...
4.1.6 Existing Means to Improve the Linearity of Signal´s Analog-to-Digital Conversion with Self-Calibration
4.1.7 Existing Methods for Reducing Nonlinearity in Flash ADCs
4.1.8 Existing Methods for Reducing Nonlinearity in Current DACs
4.1.9 Existing Methods for Reducing Nonlinearity in Pipeline ADCs
4.1.10 Principles to Improve the Linearity of Signal´s Analog-to-Digital Conversion with Self-Calibration
4.2 Conclusions
4.3 Methods of Improving the Linearity of Signal´s Analog-to-Digital Conversion with Self-Calibration
4.3.1 Method of Reducing the Nonlinearity with Self-Calibration by Correcting the Offset Error of Comparators in Flash Analog-...
4.3.2 Method of Reducing the Nonlinearity with Self-Calibration by Correcting the Current Deviation Error of Current Sources i...
4.3.3 Means of Reducing System Nonlinearity with Self-Calibration by Increasing the Linearity of Comparators in Pipeline Analo...
4.4 Conclusion
References
Chapter 5: Design of High-performance Heterogeneous Integrated Circuits
5.1 General Issues of Designing Means for High-performance Heterogeneous Integrated Circuits
5.1.1 Importance of Design Means for High-performance Heterogeneous Integrated Circuits
Structure of High-performance Heterogeneous Integrated Circuits
Design Issues of High-performance Heterogeneous Integrated Circuits
5.1.2 Current State and Issues of Design Means for High-performance Heterogeneous Integrated Circuits
Data Transfer Problems Between Component Parts in High-performance Heterogeneous ICs
Data Transmission Problems Between Clock Domains in High-performance Heterogeneous ICs
Implementation Issues of High-performance Heterogeneous IC Architecture
5.1.3 Principles of Design Means for High-performance Heterogeneous Integrated Circuits
5.2 Methods of Design for High-performance Heterogeneous Integrated Circuits
5.2.1 Method for Improving Data Transfer Between Components in High-performance Heterogeneous Integrated Circuits
Evaluation of the Effectiveness of the Method for Improving the Means of Data Transfer Between Components in High-performance ...
5.2.2 Method for Improving Data Transfer Between Clock Domains in High-performance Heterogeneous Integrated Circuits
Evaluation of the Effectiveness of the Method for Improving Data Transfer Between Clock Domains in High-performance Heterogene...
5.2.3 Implementation Method of the Architecture in High-performance Heterogeneous Integrated Circuits
Evaluation of Effectiveness of Implementation Method of the Architecture of High-performance Heterogeneous ICs
References
Chapter 6: Design of Digital Integrated Circuits by Improving the Characteristics of Digital Cells
6.1 General Issues in Design of Digital Integrated Circuits by Improving the Characteristics of Digital Cells
6.1.1 Importance of Design of Digital Integrated Circuits by Improving the Characteristics of Digital Cells
6.1.2 Current State and Issues of Design of Digital Integrated Circuits by Improving the Characteristics of Digital Cells
6.1.3 Proposed Principles for Efficient Design of Integrated Circuits by Improving the Characteristics of Digital Cells
6.2 Methods of Design of Digital Integrated Circuits by Improving the Characteristics of Digital Cells
6.2.1 Method of Optimizing the Accessibility of Standard I/O Cells
6.2.2 Enhanced Method for I/O Cell Accessibility Prediction and Design Optimization with Proposed Machine Learning
6.2.3 Optimization Method of Standard Cells for Digital Integrated Circuit Designs with Different Cell Heights
6.2.4 ``Sleep Mode´´ Integration Method of Cells Using Neural Network for Low-Power Designs
6.2.5 Method of Adding Metal Fillers for Digital IC Design Flow
References
Untitled
Index