This paper presents a methodology for designing primitive gates in a CMOS standard cell library. The topological design space of the gates is restricted to varying the p-to n-fet width ratio and the optimal ratio is determined analytically. With topology thus "xed, gate size selection is performed a
β¦ LIBER β¦
Libraries and compilers for CMOS IC design
- Publisher
- Elsevier Science
- Year
- 1993
- Tongue
- English
- Weight
- 123 KB
- Volume
- 17
- Category
- Article
- ISSN
- 0141-9331
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