A High-Performance Architecture with a M
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José M. Fernández; Félix Moreno; Juan M. Meneses
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Article
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1996
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Elsevier Science
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English
⚖ 90 KB
high-performance parallel and pipelined architecture (MViP) has been proposed for MPEG-2 coding. A macrocell for use in an ASIC has been designed and implemented using ES2 0.7 Am dual-layer-metal CMOS technology. This macrocell consists of about 120,000 equivalent gates and is able to execute, in re