At V dd of 3.3 V, the core current and power consumption are 8.5 mA and 28 mW, respectively. The divide-by-4/5 prescaler of the entire divider dominates the speed, and the additional divide-by-64 counter and digital control block working at low frequencies would not degrade the entire performance. This divider is also able to work from 400 to 2.9 GHz. Its input sensitivity of divide-by-256 and divide-by-271 is shown in Figure 8, and the results of other moduli are similar. With the redesigned input stage, the sensitivity is improved. Figure 9 shows the results of different frequencies (1.8, 2.4, and 2.9 GHz) divided by 256 in time domain, while Figure 10 exhibits the results of various moduli with 2.4 GHz input signals. There are 16 moduli or channels able to select. The peak-to-peak voltage of output waveforms is always the same.
Table 1 represents the comparisons with the former works based on the same technology. Our work has the best sensitivity at 2.4 GHz and the most moduli. While the other CML dividers are differential input, one proposed by us is single-ended. The singleended-input divider is easily combined with commercial VCOs on a board level. With the properties of low cost, high-speed operation, excellent sensitivity, and single-ended input, this divider is a good choice to apply to 2.4 GHz wireless communications.
4. Conclusions
This paper reported a 2.4 GHz low-cost high-speed single-endedinput programmable frequency divider created in standard 0.35-m CMOS technology. With 3.3 V supply, this divider with moduli of 256 -271 can operate from 400 to 2.9 GHz. The average sensitivity level is about Ϫ10 dBm and the lowest sensitivity is Ϫ25 dBm at 2.4 GHz. The power consumption of core is about 28 mW. Its single-ended character and good matching make itself easily connected to commercial single-ended Colpitts VCOs. Table 2 summarizes the performance of the prescaler and divider.