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A pipelined 32 b microprocessor with 13

A pipelined 32 b microprocessor with 13 kB of cache memory: A Berenbaum (AT&T Inf. Syst., Holmdel, NJ, USA), B W Colbry, D R Ditzel, R D Freeman, H R McLellan, M Shoji, K J O'Connor 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 34–35, 330. In German

📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 98 KB

tained on an 8.4 • 8.4 mm 2 die. The circuit has been designed for an operating frequency of 30 MHz under worst-case conditions. Architectural features include 32-32-b general-purpose registers, 48 or 64-b virtual addressing, and multiprocessor capability, including semaphore instructions and suppor