Intel Foxville/I225 2.5 Gbps Ethernet Controller - Software User Manual

✍ Scribed by Intel

• Publisher: Intel
• Year: 2020
• Tongue: English
• Leaves: 582
• Edition: 1.3
• Category: Library

✦ Synopsis

The Intel® Foxville 2.5 Gbps Ethernet Controller (Foxville) is a single port, compact, low power component that supports 2.5 GbE designs. Foxville offers a fully-integrated GbE Media Access Control (MAC) and Physical Layer (PHY) port. Foxville supports PCI Express Gen 2 x one lane [PCIe Gen2 v3.1].

Foxville enables 10M/100M/1000M/2.5G BASE-T implementations using an integrated PHY. It can be used for client and server system, in an add-on NIC or LAN on Motherboard (LOM) designs. It can also be used in various embedded applications.

✦ Table of Contents

Intel® Ethernet Controller I225
1.0 Introduction
1.1 Feature Summary
1.2 Scope
1.3 Terminology and Acronyms
1.3.1 External Specification and Documents
1.3.1.1 Network Interface Documents
1.3.1.2 Host Interface Documents
1.3.1.3 Networking Protocol Documents
1.3.1.4 Manageability Documents
1.3.1.5 Proxy Documents
1.4 Product Overview
1.4.1 Time Sensitive Networking Support
1.5 External Interface
1.5.1 PCIe Interface
1.5.2 Network Interfaces
1.5.3 Serial Flash Interface
1.5.4 SMBus Interface
1.5.5 Internal PHY
1.5.6 Foxville SKU Options
1.5.7 Software-Definable Pins (SDP) Interface (General-Purpose I/O)
1.5.8 LED Interface
1.5.9 Feature Summary
1.6 Overview of Changes Compared to Springville
1.6.1 Link Speed - 2.5 Gb/s
1.6.2 PCIe Speed
1.6.3 Manageability & Security
1.6.4 Time Sensitive Networking
1.7 Device Data Flows
1.7.1 Transmit Data Flow
1.7.2 Receive Data Flow
2.0 Pin Interface
2.1 Signal Type Definition - Abbreviations
2.2 Ethernet Media Interface
2.3 PCIe Interface
2.4 Management and SPI Flash Interfaces
2.5 LED / JTAG / UART Interface
2.6 Miscellaneous Signals
2.7 Power Supply
2.7.1 Leakage Avoidence on LAN power disconnect
3.0 Interconnects
3.1 PCIe
3.1.1 PCIe Overview
3.1.2 General Functionality
3.1.2.1 Native/Legacy
3.1.2.2 Transactions
3.1.3 Host Interface
3.1.3.1 Tag IDs
3.1.3.1.1 TAG ID Allocation for Read Transactions
3.1.3.1.2 Priority TAG for Read and Write Transactions
3.1.3.2 Completion Timeout Mechanism
3.1.3.2.1 Completion Timeout Period
3.1.4 PCI PTM Support
3.1.4.1 PTM Messages Latency and Accuracy
3.1.4.2 PTM Messages
3.1.4.3 PTM State Machine
3.1.4.4 PTM Cycles Initiation
3.1.4.5 Exceptions Handling
3.1.4.6 Reporting Format of the PTM Results
3.1.4.7 PTM Capability in the PCIe Configuration Space
3.1.5 Transaction Layer
3.1.5.1 Transaction Types Accepted by Foxville
3.1.5.1.1 Configuration Request Retry Status
3.1.5.1.2 Partial Memory Read and Write Requests
3.1.5.2 Transaction Types Initiated by Foxville
3.1.5.2.1 Data Alignment
3.1.5.2.2 Multiple Tx Data Read Requests (MULR)
3.1.5.3 Messages
3.1.5.3.1 Message Handling by Foxville (as a Receiver)
3.1.5.3.2 Message Handling by Foxville (as a Transmitter)
3.1.5.4 Ordering Rules
3.1.5.4.1 Out of Order Completion Handling
3.1.5.5 Transaction Definition and Attributes
3.1.5.5.1 Max Payload Size
3.1.5.5.2 Traffic Class (TC) and Virtual Channels (VC)
3.1.5.5.3 Relaxed Ordering
3.1.5.5.4 Snoop Not Required
3.1.5.5.5 No Snoop and Relaxed Ordering for LAN Traffic
3.1.5.5.5.1 No-Snoop Option for Payload
3.1.5.6 Flow Control
3.1.5.6.1 Foxville Flow Control Rules
3.1.5.6.2 Upstream Flow Control Tracking
3.1.5.6.3 Flow Control Update Frequency
3.1.5.6.4 Flow Control Timeout Mechanism
3.1.5.7 Error Forwarding
3.1.6 Data Link Layer
3.1.6.1 ACK/NAK Scheme
3.1.6.2 Supported DLLPs
3.1.6.3 Transmit EDB Nullifying
3.1.7 Physical Layer
3.1.7.1 Link Speed
3.1.7.2 Link Width
3.1.7.3 Polarity Inversion
3.1.7.4 Reset
3.1.7.5 Scrambler Disable
3.1.8 Error Events and Error Reporting
3.1.8.1 Mechanism in General
3.1.8.2 Error Events
3.1.8.3 Error Forwarding (TLP Poisoning)
3.1.8.4 ECRC
3.1.8.5 Partial Read and Write Requests
3.1.8.5.1 Partial Memory Accesses
3.1.8.5.2 Partial I/O Accesses
3.1.8.6 Error Pollution
3.1.8.7 Completion with Unsuccessful Completion Status
3.1.8.8 Error Reporting Changes
3.1.8.9 Completion with Unsupported Request (UR) or Completer Abort (CA)
3.1.9 Performance Monitoring
3.1.10 PCIe Power Management
3.1.11 PCIe Programming Interface
3.2 Management Interfaces
3.3 Non-Volatile Memory (NVM) Flash
3.3.1 General Overview
3.3.1.1 Flash Detection, NVM Validity Field, and Non-Secure Mode
3.3.2 Shadow RAM
3.3.2.1 Initialization from the Shadow RAM
3.3.3 NVM Clients and Interfaces
3.3.3.1 Memory Mapped Host Interface
3.3.3.2 Management Controller (MC) Interface
3.3.4 Flash Access Contention
3.3.4.1 Arbitration Between NVM Clients
3.3.5 NVM Read, Write, and Erase Sequences
3.3.5.1 Flash Erase Flow by Software or Firmware
3.3.5.2 Software or Firmware Flow to the Bit-banging Interface
3.3.5.3 Software Word Access Flow to the EEPROM-Mode Interface
3.3.5.3.1 Read Interface
3.3.5.3.2 Write Interface
3.3.5.4 Flash Program Flow via the Memory Mapped Interface
3.3.5.5 Software or Firmware Flash Program Flow via the Flash-Mode Interface
3.3.5.6 Software or Firmware Flash Read Flow via the Flash-Mode Interface
3.3.6 NVM Validity Field
3.3.7 Flash Deadlock Avoidance
3.3.8 VPD Support
3.3.9 NVM Protection and Security
3.3.9.1 Write Protection of the Shadow RAM Sectors
3.3.9.2 Write Protection of the VPD Structure
3.3.9.3 Secured NVM Structures
3.3.10 NVM Update Flows
3.3.10.1 Flow for Updating the Firmware/OROM/PHY Secured Modules
3.3.10.2 Flow for Updating a RO NVM Item
3.3.10.3 VPD Write Flows
3.3.10.3.1 First VPD Area Programming
3.3.10.3.2 VPD Area Update Flow
3.3.10.4 Flow for Updating One of the RW Legacy EEPROM Modules
3.3.11 NVM Security
3.3.11.1 Digital Signature Algorithm Details
3.3.11.2 Intel Key Generation and the Intel Code Signing System
3.3.11.3 Protected Modules
3.3.11.4 Software Requirements
3.3.11.5 Manufacturing Requirements
3.3.11.5.1 Debug and Production Keys
3.3.11.5.2 OEM Customization
3.3.11.5.3 End-of-Line Verification
3.3.11.5.4 Post-Manufacturing Physical Modification Countermeasures
3.3.12 NVM Init Flows
3.3.12.1 Hardware Auto-load from NVM
3.3.13 FLASH Wear-out Protection
3.4 Configurable I/O Pins
3.4.1 General-Purpose I/O (Software-Definable Pins)
3.4.2 Software Watchdog
3.4.2.1 Watchdog Re-arm
3.4.3 Configurable LED Outputs
3.5 Internal Voltage Regulators
3.6 Network Interfaces
3.6.1 Overview
3.6.2 MAC Functionality
3.6.2.1 Internal GMII/MII Interface
3.6.2.1.1 Other MAC/PHY Control/Status
3.6.2.2 MDIO/MDC PHY Management Interface
3.6.2.2.1 MDIC and MDICNFG Register Usage
3.6.2.3 Duplex Operation with Copper PHY
3.6.2.3.1 Full Duplex
3.6.2.3.2 8B-10B Encoding/Decoding
3.6.2.3.3 Code Groups and Ordered Sets
3.6.3 Auto-Negotiation and Link Setup Features
3.6.3.1 Copper PHY Link Configuration
3.6.3.1.1 PHY Auto-Negotiation (Speed, Duplex, Flow Control)
3.6.3.1.2 MAC Speed Resolution
3.6.3.1.2.1 Using Internal PHY Direct Link-Speed Indication
3.6.3.1.3 MAC Full Duplex Resolution
3.6.3.1.4 Using PHY Registers
3.6.3.2 Loss of Signal/Link Status Indication
3.6.4 Ethernet Flow Control (FC)
3.6.4.1 MAC Control Frames and Receiving Flow Control Packets
3.6.4.1.1 Structure of 802.3X FC Packets
3.6.4.1.2 Operation and Rules
3.6.4.1.3 Timing Considerations
3.6.4.2 PAUSE and MAC Control Frames Forwarding
3.6.4.3 Transmission of PAUSE Frames
3.6.4.3.1 Operation and Rules
3.6.4.3.2 Software Initiated PAUSE Frame Transmission
3.6.4.4 IPG Control and Pacing
3.6.4.4.1 Fixed IPG Extension
3.6.5 Loopback Support
3.6.5.1 General
3.6.5.2 Generic Loopback Flow
3.6.5.2.1 Entering the Loopback Flow
3.6.5.2.2 Exiting the Loopback Flow
3.6.5.3 MAC Loopback
3.6.5.3.1 Setting Foxville to MAC loopback Mode
3.6.5.4 PHY Loopback
3.6.5.4.1 Setting Foxville to Internal PHY loopback Mode
3.6.5.4.2 Setting Foxville Internal PHY to External Loopback Mode
3.6.5.5 Line Loopback
3.6.6 Energy Efficient Ethernet (EEE)
3.6.6.1 Conditions to Enter EEE Tx LPI
3.6.6.2 Exit of TX LPI to Active Link State
3.6.6.3 EEE Auto-Negotiation
3.6.6.4 EEE Link Level (LLDP) Capabilities Discovery
3.6.6.5 Programming Foxville for EEE Operation
3.6.6.6 EEE Statistics
3.6.7 Integrated Copper PHY Functionality
3.6.7.1 Interconnects of the Integrated PHY
3.6.7.1.1 Transmit and Receive data bus - GMII
3.6.7.1.2 Out of band MDIO signals
3.6.7.1.3 1588 related Signals
3.6.7.1.4 Dedicated Input / Output Control signals
3.6.7.2 Determining Link State
3.6.7.2.1 Auto Negotiation
3.6.7.2.2 Parallel Detection
3.6.7.2.3 Auto Cross-Over
3.6.7.2.4 10/100 MB/s Mismatch Resolution
3.6.7.2.5 Link Criteria
3.6.7.2.5.1 1000BASE-T / 2500BASE-T
3.6.7.2.5.2 100BASE-TX
3.6.7.2.5.3 10BASE-Te
3.6.7.3 SmartSpeed (Downspeed)
3.6.7.3.1 Using SmartSpeed
3.6.7.4 Flow Control
3.6.7.5 Management Data Interface
3.6.7.6 Internal PHY Low Power Operation and Power Management
3.6.7.6.1 Power Down via the PHY Register
3.6.7.6.2 Power Management State
3.6.7.6.3 Internal PHY Link Energy Detect
3.6.7.7 Advanced Diagnostics
3.6.7.7.1 Channel Frequency Response
4.0 Initialization
4.1 Power Up
4.1.1 Power-Up Sequence
4.2 Reset Operation
4.2.1 Hardware Reset Sources
4.2.1.1 Power On Reset
4.2.1.2 PCIe Reset
4.2.1.3 In-Band PCIe Reset
4.2.1.4 D3hot to D0 Transition
4.2.2 OS Software Reset
4.2.2.1 FLR
4.2.2.2 Bus Master Enable (BME)
4.3 Software Driver Reset
4.3.1 Software Reset (DEV_RST)
4.3.2 NVM Reset
4.3.3 PHY Reset
4.4 Manageability Reset Interface
4.4.1 Force TCO
4.4.2 PHY Behavior During a Manageability Session
4.5 Registers and Logic Reset Affects
4.5.1 Registers Initialization by Software
4.6 Device and Function Disable
4.6.1 General
4.6.2 Disabling Both LAN Port and PCIe Function (Device Off)
4.6.3 Disabling PCIe Function Only
4.6.4 BIOS Handling of Device Disable
4.7 Software Initialization and Diagnostics
4.7.1 Introduction
4.7.2 Power Up State
4.7.3 Initialization Sequence
4.7.4 Interrupts During Initialization
4.7.5 Software Reset and General Configuration
4.7.6 Flow Control Setup
4.7.7 Link Setup Mechanisms and Control/Status Bit Summary
4.7.7.1 PHY Initialization
4.7.7.2 MAC/PHY Link Setup
4.7.7.2.1 MAC Settings Automatically Based on Duplex and Speed Resolved by PHY (CTRL.FRCDPLX = 0b, CTRL.FRCSPD = 0b,)
4.7.8 Initialization of Statistics
4.7.9 Receive Initialization
4.7.9.1 Initialize the Receive Control Register
4.7.9.2 Dynamic Enabling and Disabling of Receive Queues
4.7.10 Transmit Initialization
4.7.10.1 Dynamic Queue Enabling and Disabling
4.7.11 Alternate MAC Address Support
4.8 Access to Shared Resources
4.8.1 Acquiring Ownership Over a Shared Resource
4.8.2 Releasing Ownership Over a Shared Resource
5.0 Power Management
5.1 General Power State Information
5.1.1 PCI Device Power States
5.1.2 PCIe Link Power States
5.2 Internal Power States
5.2.1 D0 Uninitialized State (D0u)
5.2.1.1 Entry into D0u state
5.2.2 D0active State (D0a)
5.2.2.1 Entry to D0a State
5.2.3 D3 State (PCI-PM D3hot)
5.2.3.1 Entry to D3 State
5.2.3.2 Exit from D3 State
5.2.3.3 Master Disable Via CTRL Register
5.2.4 Dr State (D3cold)
5.2.4.1 Entry to Dr State
5.2.4.2 Auxiliary Power Usage
5.2.5 Internal PHY state vs. Device State
5.2.5.1 Link Speed vs. Device Power State
5.2.5.2 PHY State vs. Device Power State
5.2.5.3 PHY State vs. Static Device Enable Option
5.2.6 Link Disconnect
5.2.7 Device Off States
5.2.7.1 Static Device Off
5.2.7.2 Dynamic Device Off
5.3 Power Limits by Certain Form Factors
5.4 Interconnects Power Management
5.4.1 PCIe Link Power Management
5.5 Wake Up
5.5.1 Advanced Power Management Wake Up
5.5.2 ACPI Power Management Wake Up
5.5.3 Wake-Up and Proxying Filters
5.5.3.1 Pre-Defined Filters
5.5.3.1.1 Directed Exact Packet
5.5.3.1.2 Directed Multicast Packet
5.5.3.1.3 Broadcast
5.5.3.1.4 Magic Packet
5.5.3.1.5 ARP/IPv4 Request Packet
5.5.3.1.6 Directed IPv4 Packet
5.5.3.1.7 Directed IPv6 Packet
5.5.3.1.8 Neighbor Solicitation (NS) and Multicast Listener Discovery (MLD) IPv6 Packets
5.5.3.2 Flexible Filters
5.5.3.2.1 IPX Diagnostic Responder Request Packet
5.5.3.2.2 Directed IPX Packet
5.5.3.2.3 Utilizing Flex Wake-Up Filters In Normal Operation
5.5.3.3 Wake Up Packet Storage
5.6 Ultra Low Power - ULP
5.6.1 Entering the ULP State
5.6.1.1 The Flow Entering the ULP State initiated by the OS
5.6.2 Exiting the ULP State
5.6.2.1 Exiting ULP by Host
5.6.2.2 Exiting ULP by CSME
5.7 Reset On LAN (RoL)
5.8 Protocol Offload (Proxying)
5.8.1 Protocol Offload Activation in D3
5.8.2 Protocol Offload Activation in D0
5.8.3 mDNS Proxy Offload
5.9 Latency Tolerance Reporting (LTR)
5.9.1 LTR Algorithm
5.9.2 Latency Tolerance Reporting
5.9.2.1 Conditions for Generating LTR Message with the Requirement Bits Cleared
5.9.2.2 Conditions for Generating LTR Message with Maximum LTR Value
5.9.2.3 Conditions for Generating LTR Message with Minimum LTR Value
5.9.2.4 Recommended Programming of the LTR Parameters
6.0 Non-Volatile Memory Map
6.1 NVM General Summary Table
6.1.1 Common and Lan Port 0 Section Summary Table
6.1.1.1 Ethernet Individual Address 0 - 0x0000
6.1.1.2 Ethernet Individual Address 1 - 0x0001
6.1.1.3 Ethernet Individual Address 2 - 0x0002
6.1.1.4 Compatibility Bytes - 0x0003
6.1.1.5 Reserved - 0x0004
6.1.1.6 Dev_starter Version - 0x0005
6.1.1.7 OEM configuration 1 - 0x0006
6.1.1.8 OEM configuration 2 - 0x0007
6.1.1.9 PBA Number 0 - 0x0008
6.1.1.10 PBA Number 1 - 0x0009
6.1.1.11 Initialization Control Word 1 - 0x000A
6.1.1.12 Subsystem ID - 0x000B
6.1.1.13 Subsystem Vendor ID - 0x000C
6.1.1.14 Device ID - 0x000D
6.1.1.15 Vendor ID - 0x000E
6.1.1.16 Initialization Control Word 2 - 0x000F
6.1.1.17 Firmware Image Pointer - 0x0010
6.1.1.18 Flash Device Size - 0x0011
6.1.1.19 EEPROM Sizing and Protected Fields - 0x0012
6.1.1.20 Initialization Control Word 4 - 0x0013
6.1.1.21 PCIe L1 Exit latencies - 0x0014
6.1.1.22 PCIe Completion Timeout Configuration - 0x0015
6.1.1.23 MSI-X Configuration - 0x0016
6.1.1.24 PCIe Init Configuration 1 - 0x0018
6.1.1.25 PCIe Init Configuration 2 - 0x0019
6.1.1.26 PCIe Init Configuration 3 - 0x001A
6.1.1.27 PCIe Control 1 - 0x001B
6.1.1.28 LED 1,3 Configuration Defaults - 0x001C
6.1.1.29 Dummy Device ID - 0x001D
6.1.1.30 Device Rev ID - 0x001E
6.1.1.31 LED 0,2 Configuration Defaults - 0x001F
6.1.1.32 Software Defined Pins Control - 0x0020
6.1.1.33 Functions Control - 0x0021
6.1.1.34 LAN Power Consumption - 0x0022
6.1.1.35 Initialization Control Word 3 - 0x0024
6.1.1.36 mDNS Records Area Offset - 0x0025
6.1.1.37 mDNS Records Area Size - 0x0026
6.1.1.38 CSR Auto Configuration Power-Up Pointer - 0x0027
6.1.1.39 PCIe Control 2 - 0x0028
6.1.1.40 PCIe Control 3 - 0x0029
6.1.1.41 CDQM Memory Base Low - 0x002A
6.1.1.42 CDQM Memory Base High - 0x002B
6.1.1.43 End of RO Area Pointer (protected area) - 0x002C
6.1.1.44 Start of RO Area Pointer (protected area) - 0x002D
6.1.1.45 Watchdog Configuration - 0x002E
6.1.1.46 VPD Pointer - 0x002F
6.1.1.47 Setup Options PCI Function - 0x0030
6.1.1.48 Configuration Customization Options PCI Function - 0x0031
6.1.1.49 PXE Version - 0x0032
6.1.1.50 IBA Capabilities - 0x0033
6.1.1.51 PCIe PHY Configuration 0 Low - 0x0034
6.1.1.52 PCIe PHY Configuration 0 High - 0x0035
6.1.1.53 iSCSI Option ROM Version - 0x0036
6.1.1.54 Alternate MAC Address Location - 0x0037
6.1.1.55 PCIe PHY Configuration 1 Low - 0x0038
6.1.1.56 PCIe PHY Configuration 1 High - 0x0039
6.1.1.57 PCIe PHY Configuration 2 Low / Reset to PCIe PHY Delay (x40us) - 0x003A
6.1.1.58 Reserved - 0x003B
6.1.1.59 PXE VLAN pointer - 0x003C
6.1.1.60 iSCSI Boot Configuration Pointer - 0x003D
6.1.1.61 Reserved - 0x003E
6.1.1.62 Checksum Word - 0x003F
6.1.1.63 Free Provisioning Area Pointer - 0x0040
6.1.1.64 Free Provisioning Area Size - 0x0041
6.1.1.65 Image Unique ID 0 - 0x0042
6.1.1.66 Image Unique ID 1 - 0x0043
6.1.1.67 PCIe L1 Substates Capability Low - 0x0044
6.1.1.68 PCIe L1 Substates Capability High - 0x0045
6.1.1.69 PCIe L1 Substates Control 1st Low - 0x0046
6.1.1.70 PCIe L1 Substates Control 1st High - 0x0047
6.1.1.71 PCIe L1 Substates Control 2nd (only lower byte taken) - 0x0048
6.1.1.72 PTM Setting - 0x0049
6.1.1.73 EXP. ROM Boot Code Section Pointer - 0x004A
6.1.1.74 ULP Capability Enable - 0x004B
6.1.1.75 Reserved - 0x004C
6.1.1.76 Reserved - 0x004D
6.1.1.77 RO Commands Version - 0x0050
6.1.1.78 Firmware Module Configuration Pointer - 0x0051
6.1.1.79 PCIe PHY Configuration 3 Low - 0x0052
6.1.1.80 PCIe PHY Configuration 3 Hi - 0x0053
6.1.1.81 PCIe PHY Configuration 4 Low - 0x0054
6.1.1.82 PCIe PHY Configuration 4 High - 0x0055
6.1.1.83 PCIe PHY Configuration 5 Low - 0x0056
6.1.1.84 PCIe PHY Configuration 5 High - 0x0057
6.1.1.85 Reserved - 0x0058
6.1.1.86 Reserved - 0x0059
6.1.1.87 Reserved - 0x005A
6.1.1.88 Reserved - 0x005B
6.1.1.89 Reserved - 0x005C
6.1.1.90 Reserved - 0x005D
6.1.1.91 Reserved - 0x005E
6.1.1.92 Reserved - 0x005F
6.1.1.93 Reserved - 0x0060
6.1.1.94 Reserved - 0x0061
6.1.1.95 Reserved - 0x0062
6.1.1.96 Reserved - 0x0063
6.1.1.97 Reserved - 0x0064
6.1.1.98 Reserved - 0x0065
6.1.1.99 Reserved - 0x0066
6.1.1.100 Reserved - 0x0067
6.1.1.101 Reserved - 0x0068
6.1.1.102 Reserved - 0x0069
6.1.1.103 Reserved - 0x006A
6.1.1.104 Reserved - 0x006B
6.1.1.105 Reserved - 0x006C
6.1.1.106 Reserved - 0x006D
6.1.1.107 Reserved - 0x006E
6.1.1.108 Reserved - 0x006F
6.1.1.109 Reserved - 0x0070
6.1.1.110 Reserved - 0x0071
6.1.1.111 Reserved - 0x0072
6.1.1.112 Reserved - 0x0073
6.1.1.113 Reserved - 0x0074
6.1.1.114 Reserved - 0x0075
6.1.1.115 Reserved - 0x0076
6.1.1.116 Reserved - 0x0077
6.1.1.117 Reserved - 0x0078
6.1.1.118 Reserved - 0x0079
6.1.1.119 Reserved - 0x007A
6.1.1.120 Reserved - 0x007B
6.1.1.121 Reserved - 0x007C
6.1.1.122 Reserved - 0x007D
6.1.1.123 Reserved - 0x007E
6.1.1.124 Reserved - 0x007F
6.1.2 Firmware Module Configuration Section Summary Table
6.1.2.1 Reserved 0x0 - 0x0000
6.1.2.2 Reserved 0x1 - 0x0001
6.1.2.3 Reserved 0x2 - 0x0002
6.1.2.4 Common Firmware Parameters pointer - 0x0003
6.1.2.5 Reserved 0x4 - 0x0004
6.1.2.6 SideBand Configuration Pointer - 0x0006
6.1.2.7 Flexible TCO Filter Configuration Pointer - 0x0007
6.1.2.8 Reserved 0x8 - 0x0008
6.1.2.9 Reserved 0x9 - 0x0009
6.1.2.10 Reserved - NC-SI Configuration Pointer - 0x000A
6.1.2.11 Traffic Types Parameters Pointer - 0x000B
6.1.2.12 Reserved 0xD - 0x000D
6.1.2.13 Reserved 0xE - 0x000E
6.1.2.14 PHY Configuration Pointer - 0x000F
6.1.3 Common Firmware Parameters Section Summary Table
6.1.3.1 Section header - 0x0000
6.1.3.2 Common Firmware Parameters 1 - 0x0001
6.1.3.3 Common Firmware Parameters 2 - 0x0002
6.1.4 PXE VLAN Configuration Section Summary Table
6.1.4.1 VLAN Block Signature - 0x0000
6.1.4.2 Version and Size - 0x0001
6.1.4.3 Port 0 VLAN Tag - 0x0002
6.1.5 RO Start Section Summary Table
6.1.5.1 Dummy word - 0x0000
6.1.6 LPG Reset CSR Auto Configuration Section Summary Table
6.1.6.1 Section Length - 0x0000
6.1.6.2 Block CRC8 - 0x0001
6.1.6.3 PCIEERRCTL Address 5BA0 - 0x0002
6.1.6.4 PCIEERRCTL LSB - 0x0003
6.1.6.5 PCIEERRCTL Data MSB - 0x0004
6.1.6.6 PCIEPHYDAT Address 4 0x5B44 - 0x0005
6.1.6.7 PCIEPHYDAT Data 0xA800A8 - 0x0006
6.1.6.8 PCIEPHYDAT Data 4 MS - 0x0007
6.1.6.9 PCIEPHYADR Address 5 0x5B40 - 0x0008
6.1.6.10 PCIEPHYADR Data 0x5E000090 - 0x0009
6.1.6.11 PCIEPHYADR Data 5 MS - 0x000A
6.1.6.12 Device Control Register Address 0 - 0x000B
6.1.6.13 Device Control Register Data LSB - 0x000C
6.1.6.14 Device Control Register Data MSB - 0x000D
6.1.6.15 EEE_SU Address - 0x000E
6.1.6.16 EEE_SU Data LSB - 0x000F
6.1.6.17 EEE_SU Data MSB - 0x0010
6.1.6.18 CSR Address - 0x0011
6.1.6.19 CSR Data LSB - 0x0012
6.1.6.20 CSR Data MSB - 0x0013
6.1.7 RO End Section Summary Table
6.1.7.1 Dummy word - 0x0000
6.1.8 SideBand Configuration Section Summary Table
6.1.8.1 Section header - 0x0000
6.1.8.2 SMBus Maximum Fragment Size - 0x0001
6.1.8.3 SMBus Notification Timeout and Flags - 0x0002
6.1.8.4 SMBus Slave Addresses - 0x0003
6.1.8.5 Reserved 0x4 - 0x0004
6.1.8.6 Reserved 0x5 - 0x0005
6.1.8.7 NC-SI Configuration #1 - 0x0006
6.1.8.8 NC-SI Configuration #2 - 0x0007
6.1.8.9 Reserved - 0x0008
6.1.8.10 MCTP UUID - Time Low LSB - 0x0009
6.1.8.11 MCTP UUID - Time Low MSB - 0x000A
6.1.8.12 MCTP UUID - Time MID - 0x000B
6.1.8.13 MCTP UUID - Time High and Version - 0x000C
6.1.8.14 MCTP UUID - Clock Seq - 0x000D
6.1.8.15 MCTP UUID - Node1 - 0x000E
6.1.8.16 MCTP UUID - Node2 - 0x000F
6.1.8.17 MCTP UUID - Node3 - 0x0010
6.1.8.18 Alternative IANA - 0x0011
6.1.8.19 NC_SI Over MCTP Message Types - 0x0012
6.1.8.20 NC_SI Over MCTP Configuration - 0x0013
6.1.8.21 MCTP Rate Limiter Configuration 1 - 0x0014
6.1.8.22 MCTP Rate Limiter Configuration 2 - 0x0015
6.1.9 Flexible TCO Filter Configuration Section Summary Table
6.1.9.1 Section Header - 0x0000
6.1.9.2 Flexible Filter Length and Control - 0x0001
6.1.10 Traffic Types Parameters Section Summary Table
6.1.10.1 Section Header - 0x0000
6.1.10.2 Traffic Type Data - 0x0001
6.1.11 PHY Configuration Section Summary Table
6.1.11.1 Section Length - 0x0000
6.1.11.2 Block CRC8 - 0x0001
6.1.11.3 SGMII ADD 1 - 0x0002
6.1.11.4 SGMII DATA 1 - 0x0003
6.1.11.5 SGMII ADD 2 - 0x0004
6.1.11.6 SGMII DATA 2 - 0x0005
6.1.11.7 SGMII ADD 3 - 0x0006
6.1.11.8 SGMII DATA 3 - 0x0007
6.1.11.9 SGMII ADD 4 - 0x0008
6.1.11.10 SGMII DATA 4 - 0x0009
6.1.11.11 SGMII ADD 1 MDIO - 0x000A
6.1.11.12 SGMII DATA 1 MDIO - 0x000B
6.1.11.13 SGMII ADD 2 MDIO - 0x000C
6.1.11.14 SGMII DATA 2 MDIO - 0x000D
6.1.11.15 SGMII ADD 3 MDIO - 0x000E
6.1.11.16 SGMII DATA 3 MDIO - 0x000F
6.1.11.17 SGMII ADD 4 MDIO - 0x0010
6.1.11.18 SGMII DATA 4 MDIO - 0x0011
6.1.11.19 Serdes PHY Number & PHY Reg Address - 0x0012
6.1.11.20 Serdes PHY Reg Data - 0x0013
6.1.11.21 Serdes PHY Number & PHY Reg Address 1 reg 18 - 0x0014
6.1.11.22 Serdes PHY 18_254 Reg Data - 0x0015
6.1.11.23 ADD - 0x0016
6.1.11.24 DATA - 0x0017
6.1.11.25 0_PHY Number & PHY Reg Address - 0x0018
6.1.11.26 0_PHY Reg Data - 0x0019
6.1.12 Alternate MAC Address Section Summary Table
6.1.12.1 Alternate MAC Address 0 - Word 0 - 0x0000
6.1.12.2 Alternate MAC Address 0 - Word 1 - 0x0001
6.1.12.3 Alternate MAC Address 0 - Word 2 - 0x0002
6.1.12.4 Alternate MAC Address 1 - Word 0 - 0x0003
6.1.12.5 Alternate MAC Address 1 - Word 1 - 0x0004
6.1.12.6 Alternate MAC Address 1 - Word 2 - 0x0005
6.1.12.7 Alternate MAC Address 2 - Word 0 - 0x0006
6.1.12.8 Alternate MAC Address 2 - Word 1 - 0x0007
6.1.12.9 Alternate MAC Address 2 - Word 2 - 0x0008
6.1.12.10 Alternate MAC Address 3 - Word 0 - 0x0009
6.1.12.11 Alternate MAC Address 3 - Word 1 - 0x000A
6.1.12.12 Alternate MAC Address 3 - Word 2 - 0x000B
6.1.13 PBA Section Summary Table
6.1.13.1 PBA Section Length - 0x0000
6.1.13.2 Word1 - 0x0001
6.1.13.3 Word2 - 0x0002
6.1.13.4 Word3 - 0x0003
6.1.13.5 Word4 - 0x0004
6.1.13.6 Word5 - 0x0005
6.1.14 iSCSI Boot Configuration Section Summary Table
6.1.14.1 iSCSI Boot Signature - 0x0430
6.1.14.2 iSCSI Block Size - 0x0431
6.1.14.3 Structure Version - 0x0432
6.1.14.4 Initiator Name[n] (0x0433 + 1n, n=0...127)
6.1.14.5 Reserved1[n] (0x04B3 + 1n, n=0...16)
6.1.14.6 Flags - 0x04C4
6.1.14.7 Initiator IP[n] (0x04C5 + 1n, n=0...1)
6.1.14.8 Subnet Mask[n] (0x04C7 + 1n, n=0...1)
6.1.14.9 Gateway IP[n] (0x04C9 + 1n, n=0...1)
6.1.14.10 Boot LUN - 0x04CB
6.1.14.11 Target IP[n] (0x04CC + 1n, n=0...1)
6.1.14.12 Target Port - 0x04CE
6.1.14.13 Target Name[n] (0x04CF + 1n, n=0...127)
6.1.14.14 Chap Password[n] (0x054F + 1n, n=0...8)
6.1.14.15 CHAP User Name[n] (0x0558 + 1n, n=0...63)
6.1.14.16 VLAN ID - 0x0598
6.1.14.17 Mutual CHAP Secret [n] (0x0599 + 1n, n=0...8)
6.1.14.18 Reserves3[n] (0x05A2 + 1n, n=0...79)
6.1.15 VPD Module Section Summary Table
6.1.16 Pointer - GPHY FW Section Summary Table
6.1.16.1 GPHY FW Area Pointer - 0x07F0
6.1.17 Pointer - SW Free Space Section Summary Table
6.1.17.1 SW Free Space Pointer - 0x07F1
6.1.18 EXP. ROM Boot Code Section Summary Table
6.1.19 GPHY SW Section Summary Table
6.1.20 CSS header Section Summary Table
6.1.20.1 moduleTypeL - 0x0000
6.1.20.2 moduleTypeH - 0x0001
6.1.20.3 headerLenL - 0x0002
6.1.20.4 headerLenH - 0x0003
6.1.20.5 headerVersionL - 0x0004
6.1.20.6 headerVersionH - 0x0005
6.1.20.7 moduleIDL - 0x0006
6.1.20.8 moduleIDH - 0x0007
6.1.20.9 moduleVendorL - 0x0008
6.1.20.10 moduleVendorH - 0x0009
6.1.21 FW_HEADER in REGMAN Section Summary Table
6.1.21.1 DateL - 0x0000
6.1.21.2 DateH - 0x0001
6.1.21.3 sizeL - 0x0002
6.1.21.4 sizeH - 0x0003
6.1.21.5 keySizeL - 0x0004
6.1.21.6 keySizeH - 0x0005
6.1.21.7 modulusSizeL - 0x0006
6.1.21.8 modulusSizeH - 0x0007
6.1.21.9 exponentSizeL - 0x0008
6.1.21.10 exponentSizeH - 0x0009
6.1.21.11 lad_srevL - 0x000A
6.1.21.12 lad_srevH - 0x000B
6.1.21.13 reserved1 - 0x000C
6.1.21.14 reserved2 - 0x000D
6.1.21.15 lad_fw_entry_offsetL - 0x000E
6.1.21.16 lad_fw_entry_offsetH - 0x000F
6.1.21.17 lad_fl_dev_offsetL - 0x0010
6.1.21.18 lad_fl_dev_offsetH - 0x0011
6.1.21.19 reserved[n] (0x0012 + 1n, n=0...35)
6.1.21.20 RSA Public Key [n] (0x0036 + 1n, n=0...127)
6.1.21.21 RSA ExponentL - 0x00B6
6.1.21.22 RSA ExponentH - 0x00B7
6.1.21.23 Encrypted SHA256 Hash[n] (0x00B8 + 1n, n=0...127)
6.1.22 FW Image Section Summary Table
6.1.23 Flash Info Section Summary Table
6.1.23.1 Flash Devices Table Version - 0x0000
6.1.23.2 Blank NVM Device ID - 0x0001
6.1.23.3 Minimum FW Code Revision - 0x0002
6.1.23.4 Number of Flash Devices - 0x0003
6.1.23.5 JEDEC_ID_L 18 - 0x0004
6.1.23.6 JEDEC_ID_H 18 - 0x0005
6.1.23.7 FLASHMODE_L 18 - 0x0006
6.1.23.8 FLASHMODE_H+unprotect 18 - 0x0007
6.1.23.9 FLASHOP_L 18 - 0x0008
6.1.23.10 FLASHOP_H 18 - 0x0009
6.1.23.11 FLASHTIME_L 18 - 0x000A
6.1.23.12 FLASHTIME_H 18 - 0x000B
6.1.23.13 JEDEC_ID_L 19 - 0x000C
6.1.23.14 JEDEC_ID_H 19 - 0x000D
6.1.23.15 FLASHMODE_L 19 - 0x000E
6.1.23.16 FLASHMODE_H+unprotect 19 - 0x000F
6.1.23.17 FLASHOP_L 19 - 0x0010
6.1.23.18 FLASHOP_H 19 - 0x0011
6.1.23.19 FLASHTIME_L 19 - 0x0012
6.1.23.20 FLASHTIME_H 19 - 0x0013
6.1.23.21 JEDEC_ID_L 20 - 0x0014
6.1.23.22 JEDEC_ID_H 20 - 0x0015
6.1.23.23 FLASHMODE_L 20 - 0x0016
6.1.23.24 FLASHMODE_H+unprotect 20 - 0x0017
6.1.23.25 FLASHOP_L 20 - 0x0018
6.1.23.26 FLASHOP_H 20 - 0x0019
6.1.23.27 FLASHTIME_L 20 - 0x001A
6.1.23.28 FLASHTIME_H 20 - 0x001B
6.1.23.29 JEDEC_ID_L 62_5 - 0x001C
6.1.23.30 JEDEC_ID_H 62_5 - 0x001D
6.1.23.31 FLASHMODE_L 62_5 - 0x001E
6.1.23.32 FLASHMODE_H+unprotect 62_5 - 0x001F
6.1.23.33 FLASHOP_L 62_5 - 0x0020
6.1.23.34 FLASHOP_H 62_5 - 0x0021
6.1.23.35 FLASHTIME_L 62_5 - 0x0022
6.1.23.36 FLASHTIME_H 62_5 - 0x0023
6.1.24 RO Updates Info Section Summary Table
6.1.24.1 RO Updates Version - 0x0000
6.1.24.2 Blank NVM Device ID - 0x0001
6.1.24.3 Minimum FW Code Revision - 0x0002
6.1.24.4 RO Updates Length - 0x0003
6.1.24.5 RO Updates Contents - 0x0004
6.1.25 CSS-signed Firmware Secured Module Section Summary Table
6.1.26 Free Provisioning Area Section Summary Table
6.1.26.1 Reserved - 0x0000
6.1.27 mDNS Records Section Summary Table
6.1.27.1 Reserved - 0x0000
6.1.28 SW Free Space Section Summary Table
6.1.28.1 Reserved - 0x0000
7.0 Inline Functions
7.1 Receive Functionality
7.1.1 L2 Packet Filtering MNG and Circuit Breaker filters
7.1.1.1 MAC Address Filtering
7.1.1.1.1 Unique (Exact) MAC Address Filters
7.1.1.1.2 Inexact MAC Address Filter
7.1.1.2 VLAN Filtering
7.1.1.3 Manageability Filtering
7.1.1.4 Size Filtering
7.1.2 Receive Queues Assignment
7.1.2.1 Queuing Method
7.1.2.2 Queue Configuration Registers
7.1.2.3 L2 Ether-type Filters
7.1.2.4 2-Tuple Filters
7.1.2.5 Flex Filters
7.1.2.6 SYN Packet Filters
7.1.2.7 VLAN Priority Filters
7.1.2.8 MAC Address Filters
7.1.2.9 Receive-Side Scaling (RSS)
7.1.2.9.1 RSS Hash Function
7.1.2.9.1.1 Hash for IPv4 with TCP
7.1.2.9.1.2 Hash for IPv4 with UDP
7.1.2.9.1.3 Hash for IPv4 without TCP
7.1.2.9.1.4 Hash for IPv6 with TCP
7.1.2.9.1.5 Hash for IPv6 with UDP
7.1.2.9.1.6 Hash for IPv6 without TCP
7.1.2.9.2 Indirection Table
7.1.2.9.3 RSS Verification Suite
7.1.2.9.3.1 IPv4
7.1.2.9.3.2 IPv6
7.1.2.9.4 Association Through MAC Address
7.1.3 Receive Data Storage
7.1.3.1 Host Buffers
7.1.3.2 On-Chip Receive Buffer
7.1.3.3 On-chip Descriptor Buffers
7.1.4 Receive Descriptors
7.1.4.1 Legacy Receive Descriptor Format
7.1.4.1.1 Legacy Receive Descriptors - Read Format
7.1.4.1.2 Legacy Receive Descriptors - Write-Back Format
7.1.4.2 Advanced Receive Descriptors
7.1.4.2.1 Advanced Receive Descriptors (RDESC) - Read Format
7.1.4.2.2 Advanced Receive Descriptors (RDESC) - Write-back Format
7.1.4.3 Receive Descriptor Fetching
7.1.4.4 Receive Descriptor Write-back
7.1.4.5 Receive Descriptor Ring Structure
7.1.4.5.1 Low Receive Descriptors Threshold
7.1.5 Header Splitting and Replication
7.1.5.1 Purpose
7.1.5.2 Description
7.1.6 Receive Packet Timestamp in Buffer
7.1.7 Receive Packet Checksum and SCTP CRC Offloading
7.1.7.1 Filters Details
7.1.7.1.1 MAC Address Filter
7.1.7.1.2 SNAP/VLAN Filter
7.1.7.1.3 IPv4 Filter
7.1.7.1.4 IPv6 Filter
7.1.7.1.5 IPv6 Extension Headers
7.1.7.1.6 UDP/TCP Filter
7.1.7.2 Receive UDP Fragmentation Checksum
7.1.7.3 SCTP Offload
7.2 Transmit Functionality
7.2.1 Packet Transmission
7.2.1.1 Transmit Data Storage
7.2.1.2 On-Chip Transmit Buffers
7.2.1.3 On-Chip descriptor Buffers
7.2.1.4 Transmit Contexts
7.2.2 Transmit Descriptors
7.2.2.1 Legacy Transmit Descriptor Format
7.2.2.1.1 Buffer Address (64)
7.2.2.1.2 Length
7.2.2.1.3 Checksum Offset and Start - CSO and CSS
7.2.2.1.4 Command Byte - CMD
7.2.2.1.5 Status – STA
7.2.2.1.6 DD (Bit 0) - Descriptor Done Status
7.2.2.1.7 VLAN
7.2.2.2 Advanced Transmit Context Descriptor
7.2.2.2.1 IPLEN (9)
7.2.2.2.2 MACLEN (7)
7.2.2.2.3 LaunchTime (30)
7.2.2.2.4 TSN_CNTX (3)
7.2.2.2.5 TUCMD (11)
7.2.2.2.6 DTYP(4)
7.2.2.2.7 DEXT(1)
7.2.2.2.8 IDX (1)
7.2.2.2.9 L4LEN (8)
7.2.2.2.10 MSS (16)
7.2.2.3 Advanced Transmit Data Descriptor
7.2.2.3.1 Address (64) / DMA Time Stamp
7.2.2.3.2 DTALEN (16)
7.2.2.3.3 PTP1 (4)
7.2.2.3.4 PTP2 (3)
7.2.2.3.5 DTYP (4)
7.2.2.3.6 DCMD (8)
7.2.2.3.7 STATUS (4)
7.2.2.3.8 IDX (1)
7.2.2.3.9 POPTS (6)
7.2.2.3.10 PAYLEN (18)
7.2.2.4 Transmit Descriptor Ring Structure
7.2.2.5 Transmit Descriptor Fetching
7.2.2.6 Transmit Descriptor Write-Back
7.2.3 Transmit Completions Head Write Back
7.2.3.1 Description
7.2.4 Checksum Offloading in Non-Segmentation Mode
7.2.4.1 IP Checksum
7.2.4.2 TCP/UDP Checksum
7.2.4.3 SCTP CRC Offloading
7.2.4.4 Checksum Supported Per Packet Types
7.2.5 TCP/UDP Segmentation
7.2.5.1 Assumptions
7.2.5.2 Transmission Process
7.2.5.2.1 TCP Segmentation Data Fetch Control
7.2.5.2.2 TCP Segmentation Write-Back Modes
7.2.5.3 TCP Segmentation Performance
7.2.5.4 Packet Format
7.2.5.5 TCP/UDP Segmentation Indication
7.2.5.6 Transmit Checksum Offloading with TCP/UDP Segmentation
7.2.5.7 TCP/UDP/IP Headers Update
7.2.5.7.1 TCP/UDP/IP Headers for the First Frames
7.2.5.7.2 TCP/UDP/IP Headers for the Subsequent Frames
7.2.5.7.3 TCP/UDP/IP Headers for the Last Frame
7.2.5.8 Data Flow
7.2.6 Multiple Transmit Queues
7.3 Interrupts
7.3.1 Interrupt Modes
7.3.1.1 MSI-X and Vectors
7.3.2 Mapping of Interrupt Causes
7.3.2.1 Legacy and MSI Interrupt Modes
7.3.2.2 MSI-X Mode
7.3.3 Legacy Interrupt Registers
7.3.3.1 Interrupt Cause Register (ICR)
7.3.3.1.1 Legacy Mode
7.3.3.1.2 Advanced Mode
7.3.3.2 Interrupt Cause Set Register (ICS)
7.3.3.3 Interrupt Mask Set/Read Register (IMS)
7.3.3.4 Interrupt Mask Clear Register (IMC)
7.3.3.5 Interrupt Acknowledge Auto-mask register (IAM)
7.3.3.6 Extended Interrupt Cause Registers (EICR)
7.3.3.6.1 MSI/INT-A Mode (GPIE.Multiple_MSIX = 0b)
7.3.3.6.2 MSI-X Mode (GPIE.Multiple_MSIX = 1b)
7.3.3.7 Extended Interrupt Cause Set Register (EICS)
7.3.3.8 Extended Interrupt Mask Set and Read Register (EIMS) & Extended Interrupt Mask Clear Register (EIMC)
7.3.3.9 Extended Interrupt Auto Clear Enable Register (EIAC)
7.3.3.10 Extended Interrupt Auto Mask Enable Register (EIAM)
7.3.3.11 GPIE Register
7.3.4 Clearing Interrupt Causes
7.3.4.1 Auto-Clear
7.3.4.2 Write to Clear
7.3.4.3 Read to Clear
7.3.5 Interrupt Moderation
7.3.6 Rate Controlled Low Latency Interrupts (LLI)
7.3.6.1 Rate Control Mechanism
7.3.7 TCP Timer Interrupt
7.3.7.1 Introduction
7.3.7.2 Description
7.3.8 Setting Interrupt Registers
7.4 802.1Q VLAN Support
7.4.1 802.1Q VLAN Packet Format
7.4.2 802.1Q Tagged Frames
7.4.3 Transmitting and Receiving 802.1Q Packets
7.4.3.1 Adding 802.1Q Tags on Transmits
7.4.3.2 Stripping 802.1Q Tags on Receives
7.4.4 802.1Q VLAN Packet Filtering
7.4.4.1 Host VLAN Filtering:
7.4.4.2 Manageability VLAN Filtering:
7.4.5 Double VLAN Support
7.4.5.1 Transmit Behavior with External VLAN
7.4.5.2 Receive Behavior with External VLAN
7.5 Time Sensitive Network Support - TSN
7.5.1 Time SYNC (IEEE1588 and IEEE 802.1AS-Rev)
7.5.1.1 PTP Time Synchronization Flow
7.5.1.2 Time-Stamp Delivery from the Master to the Slave
7.5.1.3 1588 Timer - Logic and Its programming
7.5.1.3.1 1588 Timers Logic
7.5.1.3.2 1588 Timers Logic Supporting 4 x 1588 Timers
7.5.1.3.3 Packet Time-Stamp Sampling by the Hardware
7.5.1.3.4 Receive Packet Sampling - Software Interface
7.5.1.3.5 Transmit Packet Sampling - Software Interface
7.5.1.3.6 Synchronized SDP Output to the 1588 timers
7.5.1.3.6.1 Shared Settings to all synchronized SDP output options
7.5.1.3.6.2 Synchronized Level Changed on SDP Output
7.5.1.3.6.3 Synchronized Pulse on SDP Output
7.5.1.3.6.4 Synchronized Output Clock on SDP Output
7.5.1.3.7 Synchronized SDP Input to the 1588 timers
7.5.1.3.8 Time SYNC Interrupts
7.5.2 Transmit Scheduling (802.1Qav and 802.1Qbv)
7.5.2.1 Foxville Transmit Buffer Modes
7.5.2.2 Foxville Transmit Queue Types
7.5.2.3 Transmit Pipeline in TSN Mode
7.5.2.4 Mapping User Priorities to Queues
7.5.2.5 Transmission Selection
7.5.2.6 Transmit Scheduling Latency
7.5.2.7 Credit Based Shaping - 802.1Qav
7.5.2.7.1 Credit Base Shaping and Qbv
7.5.2.8 Basic Scheduling
7.5.2.8.1 Basic Scheduling - Parameters
7.5.2.9 Time Aware Shaper - 802.1Qbv
7.5.2.9.1 Time Aware Shaper - Parameters
7.5.2.9.2 Time Aware Shaper for whole Packets Transmission - Flow
7.5.2.9.3 Time Aware Shaper for Preempted Fragments - Flow
7.5.2.9.3.1 Packet Data Fetch Time
7.5.2.9.3.2 Initialization the Qbv Base and Cycle Time Registers
7.5.2.9.3.3 The First Packet on Each Qbv Cycle
7.5.3 Preemption and Interspersing Express Traffic (802.3br)
7.5.3.1 Preemption - 802.3br
7.5.3.1.1 mPacket Format
7.5.3.1.2 Transmit Operation When Preemption is Enabled
7.5.3.1.3 Receive Operation When Preemption is Enabled
7.5.3.1.4 Receive Packet Buffers When Preemption is Enabled
7.5.3.1.5 Receive Packet Classification when Preemption is Enabled
7.5.3.1.6 Preemption and Wake Up functionality
7.5.3.1.7 Preemption Init Flow
7.5.3.1.8 Debug Registers and Statistic Counters
7.5.4 TSN Configuration
7.5.5 PTP Packet Structure - Background
7.6 Statistic Counters
7.6.1 IEEE 802.3 Clause 30 Management
7.6.2 OID_GEN_STATISTICS
7.6.3 RMON
7.6.4 Linux net_device_stats
7.6.5 Statistics Hierarchy
7.7 Memory Error Correction and Detection
7.7.1 Software Recovery From Parity Error Event
7.7.1.1 Recovery from PCIe Parity Error Event
7.7.1.2 Recovery from DMA Parity Error Event
7.7.1.3 Recovery from LAN Port Parity Error Event
7.7.1.4 Recovery from Management Parity Error Event
8.0 Programming Interface
8.1 Introduction
8.1.1 Memory, I/O Address and Configuration Decoding
8.1.1.1 Memory-Mapped Access to Internal Registers and Memories
8.1.1.2 Memory-Mapped Access to Flash
8.1.1.3 Memory-Mapped Access to MSI-X Tables
8.1.1.4 Memory-Mapped Access to Expansion ROM
8.1.1.5 I/O-Mapped Access to Internal Registers and Memories
8.1.1.5.1 IOADDR (I/O Offset 0x00)
8.1.1.5.2 IODATA (I/O Offset 0x04)
8.1.1.5.3 Undefined I/O Offsets
8.1.1.6 Configuration Access to Internal Registers and Memories
8.1.2 Register Conventions
8.1.2.1 Registers Byte Ordering
8.1.3 Register Summary
8.1.3.1 Alias Addresses
8.1.4 MSI-X BAR Register Summary
8.2 General Register Descriptions
8.2.1 Device Control Register - CTRL (0x00000; RW)
8.2.2 Device Status Register - STATUS (0x0008; RO)
8.2.3 Extended Device Control Register - CTRL_EXT (0x0018; RW)
8.2.4 Media Dependent Interface (MDI) Control Register - MDIC (0x0020; RW)
8.2.5 LED Control - LEDCTL (0x0E00; RW)
8.2.6 MDC/MDIO Configuration Register - MDICNFG (0x0E04; RW)
8.2.7 Copper/Fiber Switch Control - CONNSW (0x0034; RW)
8.2.8 VLAN Ether Type - VET (0x0038; RW)
8.3 Internal Packet Buffer Size Registers
8.3.1 RX Packet Buffer Size - RXPBSIZE (0x2404; RW)
8.3.2 Transmit Packet Buffer Size - TXPBSIZE (0x3404; RW)
8.4 NVM Registers Descriptions
8.4.1 EEPROM-Mode Control Register - EEC (0x12010; RW)
8.4.2 EEPROM-Mode Read Register - EERD (0x12014; RW)
8.4.3 EEPROM-Mode Write Register – EEWR (0x12018; RW)
8.4.4 Flash Access - FLA (0x1201C; RW)
8.4.5 Flash Security - FL_SECU (0x12114; RO to host, RW to FW)
8.4.6 Shadow RAM Information Register - SHADOWINF (0x012068; RO)
8.4.7 Manageability EEPROM-Mode Control Register – EEMNGCTL (0x12030; RO to Host, RW to FW)
8.4.8 Flash Firmware Code Update – FLFWUPDATE (0x12108; RW)
8.4.9 Software Flash Control Register - FLSWCTL (0x12048; RW)
8.4.10 Software Flash Burst Data Register - FLSWDATA (0x1204C; RW)
8.4.11 Software Flash Burst Access Counter - FLSWCNT (0x12050; RW)
8.4.12 VPD Diagnostic Register 0 - VPDDIAG (0x5B3C; RO to Host, RW to FW)
8.4.13 VPD Diagnostic Register 1 - VPDDIAG1 (0x10208; RO) DMA
8.5 Flow Control Register Descriptions
8.5.1 Flow Control Address Low - FCAL (0x0028; RW)
8.5.2 Flow Control Address High - FCAH (0x002C; RW)
8.5.3 Flow Control Type - FCT (0x0030; RW)
8.5.4 Flow Control Transmit Timer Value - FCTTV (0x0170; RW)
8.5.5 Flow Control Receive Threshold Low - FCRTL0 (0x2160; RW)
8.5.6 Flow Control Receive Threshold High - FCRTH0 (0x2168; RW)
8.5.7 Flow Control Refresh Threshold Value - FCRTV (0x2460; RW)
8.5.8 Flow Control Status - FCSTS0 (0x2464; RO)
8.6 PCIe Register Descriptions
8.6.1 PCIe Control - GCR (0x5B00; RW)
8.6.2 Function Active and Power State to MNG - FACTPS (0x5B30; RO)
8.6.3 Mirrored Revision ID - MREVID (0x5B64; RW)
8.6.4 PCIe Control Extended Register - GCR_EXT (0x5B6C; RW)
8.6.5 PTM Control - PTM_CTRL (0x12540; RW)
8.6.6 PTM Status - PTM_STAT (0x12544; RW1C)
8.6.7 PTM Start Time - PTM_STRT_TIME (0x12548; RW)
8.6.8 PTM Cycle Control - PTM_CYCLE_CTRL (0x1254C; RW)
8.6.9 PCIe Digital Delay - PCIe_DIG_Delay (0x12550; RW)
8.6.10 PCIe PHY Delay - PCIe_PHY_DELAY (0x12554; RW)
8.6.11 T1 on Timer 0 Low - PTM_T1_TIM0_L (0x12558; RO)
8.6.12 T1 on Timer 0 High - PTM_T1_TIM0_H (0x1255C; RO)
8.6.13 T4 minus T1 on Previous PTM Cycle - PTM_Prev_T4m1 (0x12578; RO)
8.6.14 T4 minus T1 on this PTM Cycle - PTM_Curr_T4m1 (0x1257C; RO)
8.6.15 T3 minus T2 on Previous PTM Cycle - PTM_Prev_T3m2 (0x12580; RO)
8.6.16 T2 on Previous PTM Cycle Low - PTM_Prev_T2_L (0x12584; RO)
8.6.17 T2 on Previous PTM Cycle High - PTM_Prev_T2_H (0x12588; RO)
8.6.18 T2 on this PTM Cycle Low - PTM_Curr_T2_L (0x1258C; RO)
8.6.19 T2 on this PTM Cycle High - PTM_Curr_T2_H (0x12590; RO)
8.6.20 PTM PCIe Link Delay - PTM_TDELAY (0x12594; RO)
8.6.21 Time Params for L12 - PCIE_L12_TIMES (0x125A4; RW)
8.6.22 PCIE to P10 state - PCIE_TIMES_2P10 (0x125A8; RW)
8.6.23 PCIE Ext CLK Warm up - PCIE_L1_EXTCLK (0x125B0; RW)
8.7 Semaphore Registers
8.7.1 Software Semaphore - SWSM (0x5B50; RW)
8.7.2 Firmware Semaphore - FWSM (0x5B54; RO to Host, RW to FW)
8.7.3 Software–Firmware Synchronization - SW_FW_SYNC (0x5B5C; RWM)
8.8 Interrupt Register Descriptions
8.8.1 Extended Interrupt Cause - EICR (0x1580; RC/W1C)
8.8.2 Extended Interrupt Cause Set - EICS (0x1520; WO)
8.8.3 Extended Interrupt Mask Set/Read - EIMS (0x1524; RWM)
8.8.4 Extended Interrupt Mask Clear - EIMC (0x1528; WO)
8.8.5 Extended Interrupt Auto Clear - EIAC (0x152C; RW)
8.8.6 Extended Interrupt Auto Mask Enable - EIAM (0x1530; RW)
8.8.7 Interrupt Cause Read Register - ICR (0x1500; RC/W1C)
8.8.8 Interrupt Cause Set Register - ICS (0x1504; WO)
8.8.9 Interrupt Mask Set/Read Register - IMS (0x1508; RW)
8.8.10 Interrupt Mask Clear Register - IMC (0x150C; WO)
8.8.11 Interrupt Acknowledge Auto Mask Register - IAM (0x1510; RW)
8.8.12 Interrupt Throttle - EITR (0x1680 + 4n [n = 0...4]; RW)
8.8.13 Interrupt Vector Allocation Registers - IVAR (0x1700 + 4n [n=0...1]; RW)
8.8.14 Interrupt Vector Allocation Registers - MISC IVAR_MISC (0x1740; RW)
8.8.15 General Purpose Interrupt Enable - GPIE (0x1514; RW)
8.8.16 PCIe Interrupt Cause - PICAUSE (0x5B88; RW1/C)
8.8.17 PCIe Interrupt Enable - PIENA (0x5B8C; RW)
8.8.18 MSI-X PBA Clear - PBACL (0x5B68; RW1C)
8.9 Receive Register Descriptions
8.9.1 Receive Control Register - RCTL (0x0100; RW)
8.9.2 Packet Split Receive Type - PSRTYPE (0x5480 + 4n [n=0...3]; RW)
8.9.3 Receive Descriptor Base Address Low - RDBAL (0xC000 + 0x40n [n=0...3]; RW)
8.9.4 Receive Descriptor Base Address High - RDBAH (0xC004 + 0x40n [n=0...3]; RW)
8.9.5 Receive Descriptor Ring Length - RDLEN (0xC008 + 0x40n [n=0...3]; RW)
8.9.6 Split and Replication Receive Control - SRRCTL (0xC00C + 0x40n [n=0...3]; RW)
8.9.7 Receive Descriptor Head - RDH (0xC010 + 0x40n [n=0...3]; RW)
8.9.8 Receive Descriptor Tail - RDT (0xC018 + 0x40n [n=0...3]; RW)
8.9.9 Receive Descriptor Control - RXDCTL (0xC028 + 0x40n [n=0...3]; RW)
8.9.10 Receive Checksum Control - RXCSUM (0x5000; RW)
8.9.11 Receive Long Packet Maximum Length - RLPML (0x5004; RW)
8.9.12 Receive Filter Control Register - RFCTL (0x5008; RW)
8.9.13 Multicast Table Array - MTA (0x5200 + 4n [n=0...127]; RW)
8.9.14 Receive Address Low - RAL (0x5400 + 8n [n=0...15]; RW)
8.9.15 Receive Address High - RAH (0x5404 + 8n [n=0...15]; RW)
8.9.16 VLAN Priority Queue Filter VLANPQF (0x55B0;RW)
8.9.17 VLAN Filter Table Array - VFTA (0x5600 + 4n [n=0...127]; RW)
8.9.18 Multiple Receive Queues Command Register - MRQC (0x5818; RW)
8.9.19 RSS Random Key Register - RSSRK (0x5C80 + 4n [n=0...9]; RW)
8.9.20 Redirection Table - RETA (0x5C00 + 4n [n=0...31]; RW)
8.10 Filtering Register Descriptions
8.10.1 Immediate Interrupt RX - IMIR (0x5A80 + 4n [n=0...7]; RW)
8.10.2 Immediate Interrupt Rx Ext. - IMIREXT (0x5AA0 + 4n [n=0...7]; RW)
8.10.3 2-tuples Queue Filter - TTQF (0x59E0 + 4n[n=0...7]; RW)
8.10.4 Immediate Interrupt Rx VLAN Priority - IMIRVP (0x5AC0; RW)
8.10.5 SYN Packet Queue Filter - SYNQF (0x55FC; RW)
8.10.6 EType Queue Filter - ETQF (0x5CB0 + 4n[n=0...7]; RW)
8.11 Transmit Register Descriptions
8.11.1 Transmit Control Register - TCTL (0x0400; RW)
8.11.2 Transmit Control Extended - TCTL_EXT (0x0404; RW)
8.11.3 Transmit IPG Register - TIPG (0x0410; RW)
8.11.4 Retry Buffer Control - RETX_CTL (0x041C; RW)
8.11.5 DMA TX Control - DTXCTL (0x3590; RW)
8.11.6 DMA TX TCP Flags Control Low - DTXTCPFLGL (0x359C; RW)
8.11.7 DMA TX TCP Flags Control High - DTXTCPFLGH (0x35A0; RW)
8.11.8 DMA TX Max Total Allow Size Requests - DTXMXSZRQ (0x3540; RW)
8.11.9 DMA TX Maximum Packet Size - DTXMXPKTSZ (0x355C; RW)
8.11.10 Transmit Descriptor Base Address Low - TDBAL (0xE000 + 0x40n [n=0...3]; RW)
8.11.11 Transmit Descriptor Base Address High - TDBAH (0xE004 + 0x40n [n=0...3]; RW)
8.11.12 Transmit Descriptor Ring Length - TDLEN (0xE008 + 0x40n [n=0...3]; RW)
8.11.13 Transmit Descriptor Head - TDH (0xE010 + 0x40n [n=0...3]; RW)
8.11.14 Transmit Descriptor Tail - TDT (0xE018 + 0x40n [n=0...3]; RW)
8.11.15 Transmit Descriptor Control - TXDCTL (0xE028 + 0x40n [n=0...3]; RW)
8.11.16 Tx Descriptor Completion Write-Back Address Low - TDWBAL (0xE038 + 0x40n [n=0...3]; RW)
8.11.17 Tx Descriptor Completion Write-Back Address High - TDWBAH (0xE03C + 0x40n [n=0...3];RW)
8.12 Transmit Scheduling Registers
8.12.1 Tx Qav Hi Credit - TQAVHC (0x300C+ 0x40n [n=0...1];RW)
8.12.2 Tx Qav Control TQAVCTRL (0x3570; RW)
8.12.3 Transmit Queue Control - TXQCTL[n] (0x3344 + 4n, n=0...3; RW)
8.12.4 Tx Qav Credit Control TQAVCC[n] (0x3004, 0x3044;RW)
8.12.5 Tx Arbitration Control TxARB (0x3354;RW)
8.12.6 Transmit Scheduling Offset - GTxOFFSET (0x3310; RW)
8.12.7 Scheduling Base Time Register Low - BASET_L (0x3314; RW)
8.12.8 Scheduling Base Time Register High - BASET_H (0x3318; RW)
8.12.9 Qbv Cycle Time - QbvCycleT (0x331C; RW)
8.12.10 Shadow Qbv Cycle Time - QbvCycleT_S (0x3320; RW)
8.12.11 Qbv Start Time - StQT (0x3324 + 0x4n [n=0...3]; RW)
8.12.12 Qbv End Time - EndQT (0x3334 + 0x4n [n=0...3]; RW)
8.13 DCA and TPH Register Descriptions
8.13.1 Rx DCA Control Registers - RXCTL (0xC014 + 0x40n [n=0...3]; RW)
8.13.2 Tx DCA Control Registers - TXCTL (0xE014 + 0x40n [n=0...3]; RW)
8.14 Timer Registers Description
8.14.1 Watchdog Setup - WDSTP (0x1040; RW)
8.14.2 Watchdog Software Device Status - WDSWSTS (0x1044; RW)
8.14.3 Free Running Timer - FRTIMER (0x1048; RWM)
8.14.4 TCP Timer - TCPTIMER (0x104C; RW)
8.15 Time Sync Register Descriptions
8.15.1 Rx Time Sync Control Register - TSYNCRXCTL (0xB620;RW)
8.15.2 Tx Time Sync Control Register - TSYNCTXCTL (0xB614; RW)
8.15.3 Rx Time Sync Control Register - DOM2TIMER (0xB678; RW)
8.15.4 Tx Timestamp Value Low 0 - TXSTMPL_0 (0xB618;RO)
8.15.5 Tx Timestamp 0 Value High - TXSTMPH_0 (0xB61C; RO)
8.15.6 System Time Register Residue 0 - SYSTIMR_0 (0xB6F8; RW)
8.15.7 System Time Register Low 0 - SYSTIML_0 (0xB600; RW)
8.15.8 System Time Register High 0 - SYSTIMH_0 (0xB604; RW)
8.15.9 System Time Register Tx MS 0 - SYSTIMTM_0 (0xB6FC; RW)
8.15.10 Increment Attributes Register 0 - TIMINCA_0 (0xB608; RW)
8.15.11 Time Adjustment Offset Register 0 - TIMADJ_0 (0xB60C; RW)
8.15.12 System Time Registers for Timers 1 ... 3
8.15.13 TimeSync Auxiliary Control Register - TSAUXC (0xB640; RW)
8.15.14 Target Time Register 0 Low - TRGTTIML0 (0xB644; RW)
8.15.15 Target Time Register 0 High - TRGTTIMH0 (0xB648; RW)
8.15.16 Target Time Register 1 Low - TRGTTIML1 (0xB64C; RW)
8.15.17 Target Time Register 1 High - TRGTTIMH1 (0xB650; RW)
8.15.18 Frequency Out 0 Control Register FREQOUT0 (0xB654; RW)
8.15.19 Frequency Out 1 Control Register - FREQOUT1 (0xB658; RW)
8.15.20 Auxiliary Time Stamp 0 Register Low - AUXSTMPL0 (0xB65C; RW)
8.15.21 Auxiliary Time Stamp 0 Register High -AUXSTMPH0 (0xB660; RO)
8.15.22 Auxiliary Time Stamp 1 Register Low AUXSTMPL1 (0xB664; RW)
8.15.23 Auxiliary Time Stamp 1 Register High - AUXSTMPH1 (0xB668; RO)
8.15.24 Time Sync RX Configuration - TSYNCRXCFG (0x5F50; RW)
8.15.25 Time Sync SDP Configuration Register - TSSDP (0x003C; RW)
8.16 Time Sync Interrupt Registers
8.16.1 Time Sync Interrupt Cause Register - TSICR (0xB66C; RC/W1C)
8.16.2 Time Sync Interrupt Mask Register - TSIM (0xB674; RW)
8.17 Time Sync - Preemption Statistics
8.17.1 Good TX Preempted Packets - PRMPTDTCNT (0x4280; RC)
8.17.2 TX Preemption event counter - PRMEVNTTCNT (0x4298; RC)
8.17.3 Good RX Preempted Packets - PRMPTDRCNT (0x4284; RC)
8.17.4 RX Preemption event counter - PRMEVNTRCNT (0x429C; RC)
8.17.5 Good TX Preemptable Packets - PRMPBLTCNT (0x4288; RC)
8.17.6 Good RX Preemptable Packets - PRMPBLRCNT ( 0x428C; RC)
8.17.7 Good TX Express Packets - PRMEXPTCNT (0x4290; RC)
8.17.8 Good RX Express Packets - PRMEXPRCNT (0x4294; RC)
8.17.9 Preemption Exception Counter - PRMEXCPRCNT (0x42A0; RC)
8.18 Statistics Register Descriptions
8.18.1 CRC Error Count - CRCERRS (0x4000; RC)
8.18.2 Alignment Error Count - ALGNERRC (0x4004; RC)
8.18.3 RX Error Count - RXERRC (0x400C; RC)
8.18.4 Missed Packets Count - MPC (0x4010; RC)
8.18.5 Single Collision Count - SCC (0x4014; RC)
8.18.6 Excessive Collisions Count - ECOL (0x4018; RC)
8.18.7 Multiple Collision Count - MCC (0x401C; RC)
8.18.8 Late Collisions Count - LATECOL (0x4020; RC)
8.18.9 Collision Count - COLC (0x4028; RC)
8.18.10 Receive Error Count - RERC (0x402C; RC)
8.18.11 Defer Count - DC (0x4030; RC)
8.18.12 Transmit with No CRS - TNCRS (0x4034; RC)
8.18.13 Host Transmit Discarded Packets by MAC Count - HTDPMC (0x403C; RC)
8.18.14 Receive Length Error Count - RLEC (0x4040; RC)
8.18.15 XON Received Count - XONRXC (0x4048; RC)
8.18.16 XON Transmitted Count - XONTXC (0x404C; RC)
8.18.17 XOFF Received Count - XOFFRXC (0x4050; RC)
8.18.18 XOFF Transmitted Count - XOFFTXC (0x4054; RC)
8.18.19 FC Received Unsupported Count - FCRUC (0x4058; RC)
8.18.20 Packets Received [64 Bytes] Count - PRC64 (0x405C; RC)
8.18.21 Packets Received [65–127 Bytes] Count - PRC127 (0x4060; RC)
8.18.22 Packets Received [128–255 Bytes] Count - PRC255 (0x4064; RC)
8.18.23 Packets Received [256–511 Bytes] Count - PRC511 (0x4068; RC)
8.18.24 Packets Received [512–1023 Bytes] Count - PRC1023 (0x406C; RC)
8.18.25 Packets Received [1024 to Max Bytes] Count - PRC1522 (0x4070; RC)
8.18.26 Good Packets Received Count - GPRC (0x4074; RC)
8.18.27 Broadcast Packets Received Count - BPRC (0x4078; RC)
8.18.28 Multicast Packets Received Count - MPRC (0x407C; RC)
8.18.29 Good Packets Transmitted Count - GPTC (0x4080; RC)
8.18.30 Good Octets Received Count - GORCL (0x4088; RC)
8.18.31 Good Octets Received Count - GORCH (0x408C; RC)
8.18.32 Good Octets Transmitted Count - GOTCL (0x4090; RC)
8.18.33 Good Octets Transmitted Count - GOTCH (0x4094; RC)
8.18.34 Receive No Buffers Count - RNBC (0x40A0; RC)
8.18.35 Receive Undersize Count - RUC (0x40A4; RC)
8.18.36 Receive Fragment Count - RFC (0x40A8; RC)
8.18.37 Receive Oversize Count - ROC (0x40AC; RC)
8.18.38 Receive Jabber Count - RJC (0x40B0; RC)
8.18.39 Management Packets Received Count - MNGPRC (0x40B4; RC)
8.18.40 Management Packets Dropped Count - MPDC (0x40B8; RC)
8.18.41 Management Packets Transmitted Count - MNGPTC (0x40BC; RC)
8.18.42 BMC2OS Packets Sent by MC - B2OSPC (0x8FE0; RC)
8.18.43 BMC2OS Packets Received by Host - B2OGPRC (0x4158; RC)
8.18.44 OS2BMC Packets Received by MC - O2BGPTC (0x8FE4; RC)
8.18.45 OS2BMC Packets Transmitted by Host - O2BSPC (0x415C; RC)
8.18.46 Total Octets Received (Hi) - TORL (0x40C0; RC)
8.18.47 Total Octets Received - TORH (0x40C4; RC)
8.18.48 Total Octets Transmitted - TOTL (0x40C8; RC)
8.18.49 Total Octets Transmitted (Hi) - TOTH (0x40CC; RC)
8.18.50 Total Packets Received - TPR (0x40D0; RC)
8.18.51 Total Packets Transmitted - TPT (0x40D4; RC)
8.18.52 Packets Transmitted [64 Bytes] Count - PTC64 (0x40D8; RC)
8.18.53 Packets Transmitted [65-127 Bytes] Count - PTC127 (0x40DC; RC)
8.18.54 Packets Transmitted [128-255 Bytes] Count - PTC255 (0x40E0; RC)
8.18.55 Packets Transmitted [256-511 Bytes] Count - PTC511 (0x40E4; RC)
8.18.56 Packets Transmitted [512-1023 Bytes] Count - PTC1023 (0x40E8; RC)
8.18.57 Packets Transmitted [1024 Bytes or Greater] Count - PTC1522 (0x40EC; RC)
8.18.58 Multicast Packets Transmitted Count - MPTC (0x40F0; RC)
8.18.59 Broadcast Packets Transmitted Count - BPTC (0x40F4; RC)
8.18.60 TCP Segmentation Context Transmitted Count - TSCTC (0x40F8; RC)
8.18.61 Interrupt Assertion Count - IAC (0x4100; RC)
8.18.62 Rx Packets to Host Count - RPTHC (0x4104; RC)
8.18.63 EEE TX LPI Count - TLPIC (0x4148; RC)
8.18.64 EEE RX LPI Count - RLPIC (0x414C; RC)
8.18.65 Host Good Packets Transmitted Count-HGPTC (0x4118; RC)
8.18.66 Receive Descriptor Minimum Threshold Count-RXDMTC (0x4120; RC)
8.18.67 Host Good Octets Received Count - HGORCL (0x4128; RC)
8.18.68 Host Good Octets Received Count - HGORCH (0x412C; RC)
8.18.69 Host Good Octets Transmitted Count (Lo) - HGOTCL (0x4130; RC)
8.18.70 Host Good Octets Transmitted Count - HGOTCH (0x4134; RC)
8.18.71 Length Errors Count Register - LENERRS (0x4138; RC)
8.18.72 Management Full Buffer Drop Packet Count - MNGFBDPC (0x4154; RC/W)
8.19 Per Queue Statistical Counters
8.19.1 Per Queue Good Packets Received Count - PQGPRC (0x10010 + n0x100 [n=0...3]; RW)
8.19.2 Per Queue Good Packets Transmitted Count - PQGPTC (0x10014 + n0x100 [n=0...3]; RW)
8.19.3 Per Queue Good Octets Received Count - PQGORC (0x10018 + n0x100 [n=0...3]; RW)
8.19.4 Per Queue Good Octets Transmitted Count - PQGOTC (0x10034 + n0x100 [n=0...3]; RW)
8.19.5 Per Queue Multicast Packets Received Count - PQMPRC (0x10038 + n0x100 [n=0...3]; RW)
8.19.6 Receive Queue Drop Packet Count - RQDPC (0xC030 + 0x40n [n=0...3]; RW)
8.19.7 Transmit Queue Drop Packet Count - TQDPC (0xE030 + 0x40n [n=0...3]; RW)
8.20 Wake Up Control Register Descriptions
8.20.1 Wake Up Control Register - WUC (0x5800; RW)
8.20.2 Wakeup Filter Control Register - WUFC (0x5808; RW)
8.20.3 Wakeup Filter Control Register Extended - WUFC_EXT (0x0000580C; RW) MAC
8.20.4 Wake Up Status Register - WUS (0x5810; RW1C)
8.20.5 Wakeup Status Register Extended - WUS_EXT (0x5814; RW1/C)
8.20.6 Wake Up Packet Length - WUPL (0x5900; RO)
8.20.7 Wake Up Packet Memory - WUPM (0x5A00 + 4n [n=0...31]; RO)
8.20.8 Wakeup Packet Memory Extended - WUPM_EXT[n] (0xB800 + 0x4n, n=0...431; RO) MAC
8.20.9 Proxying Filter Control Register - PROXYFC (0x5F60; RW)
8.20.10 Proxying Status Register - PROXYS (0x5F64; RW1C)
8.20.11 Proxying Filter Control Extended Register - PROXYFCEX (0x5590; RW)
8.20.12 Proxying Extended Status Register - PROXYEXS (0x5594; RW1C)
8.20.13 Wake Flex UDP/TCP Ports Filter - WFUTPF (0x5500 + 4n [n=0...31]; RW)
8.20.14 Range Flex UDP/TCP Port Filter - RFUTPF (0x5580; RW)
8.20.15 Range and Wake Port Filter Control - RWPFC (0x5584; RW)
8.20.16 Wake Flex UDP/TCP Ports Status - WFUTPS (0x5588, RW1C)
8.20.17 Wake Control Status - WCS (0x558C, RW1C)
8.20.18 IP Address Valid - IPAV (0x5838; RW)
8.20.19 IPv4 Address Table - IP4AT (0x5840 + 8n [n=0...3]; RW)
8.20.20 IPv6 Address Table - IP6AT (0x5880 + 4n [n=0...3]; RW)
8.20.21 Flexible Host Filter Table Registers - FHFT (0x9000 + 256n [n=0...3]; RW)
8.20.21.1 Flex Filter - Example
8.20.21.2 Flex Filter Queueing Field
8.20.22 Flexible Host Filter Table Extended Registers - FHFT_EXT (0x9A00 + 256n [n=0...3]; RW)
8.20.23 Flex Filter indirect table select - FHFTSL (0x5804; RW) MAC
8.21 Management Register Descriptions
8.21.1 Management Control Register - MANC (0x5820; RW)
8.21.2 Management Only Traffic Register - MNGONLY (0x5864; RW)
8.22 Host Slave Interface Registers Description
8.22.1 Host Slave Command Interface to Manageability Firmware
8.22.1.1 Host Slave Command I/F Flow
8.22.2 HOST Interface Control Register - HICR (0x8F00; RW)
8.22.3 Firmware Software Mailbox Register- FWSWMB (0x8F04; RW)
8.22.4 Firmware Status Register - FWSTS (0x8F0C; RW)
8.22.5 Software Status Register - SWSR (0x8F10; RW)
8.22.6 Message to Manageability Register - MSG2MNG (0x8F50; RCW) MNG
8.22.7 Message to Manageability Mask Register - MSKMSG2MNG (0x8F54; RW) MNG
8.22.8 Host Interface Buffer Base Address - HIBBA (0x8F40; RW)
8.22.9 Host Interface Buffer Maximum Offset - HIBMAXOFF (0x8F44; RO)
8.23 Memory Error Registers Description
8.23.1 Parity and ECC Error Indication - PEIND (0x1084; RC)
8.23.2 Parity and ECC Indication Mask - PEINDM (0x1088; RW)
8.23.3 Packet Buffer ECC Status - PBECCSTS (0x245c; RW)
8.23.4 PCIe Parity Control Register - PCIEERRCTL (0x5BA0; RW)
8.23.5 PCIe Parity Status Register - PCIEERRSTS (0x5BA8; RW1C)
8.23.6 PCIe ECC Control Register - PCIEECCCTL (0x5BA4; RW)
8.23.7 PCIe ECC Status Register - PCIEECCSTS (0x5BAC; RW1C)
8.23.8 PCIe ACL0 and ACL1 Register - PCIACL01 (0x5B7C; RW)
8.23.9 PCIe ACL2 and ACL3 Register - PCIACL23 (0x5B80; RW to FW)
8.23.10 LAN Port Parity Error Control Register - LANPERRCTL (0x5F54; RW)
8.23.11 LAN Port Parity Error Inject Register - LANPERRINJ (0x5F5C; SC)
8.23.12 LAN Port Parity Error Status Register - LANPERRSTS (0x5F58; RW1C)
8.23.13 Management Parity Configuration Register - MNGPARCTL (0x8F20; RW)
8.23.14 Management Parity Status Register - MNGPARSTS (0x8F24; RW1/C)
8.23.15 Management ECC Configuration Register - MNGECCCTL (0x8F28; RW)
8.23.16 Management ECC Status Register - MNGECCSTS (0x8F2C; RW1/ C)
8.23.17 DMA Receive Parity and ECC Control - DRPARC (0x3F04; RW/SC)
8.24 Power Management Register Description
8.24.1 DMA Coalescing Management Threshold - DMCMNGTH (0x8F30;RW)
8.24.2 Latency Tolerance Reporting (LTR) Minimum Values - LTRMINV (0x5BB0; RW)
8.24.3 Latency Tolerance Reporting (LTR) Maximum Values - LTRMAXV (0x5BB4; RW)
8.24.4 Latency Tolerance Reporting (LTR) Control - LTRC (0x01A0; RW)
8.24.5 Energy Efficient Ethernet (EEE) Register - EEER (0x0E30; RW)
8.24.6 Energy Efficient Ethernet (EEE) Setup Register - EEE_SU (0x0E34; RW)
8.24.7 Energy Efficient Ethernet (EEE) 2.5Gb/s Setup Register - EEE_SU_2P5 (0x0E3C; RW)
8.25 PHY Software Interface
8.25.1 Internal PHY Configuration - IPCNFG (0x0E38, RW)
8.25.2 PHY Power Management - PHPM (0x0E14, RW)
8.26 PHY MDIO Registers
9.0 PCIe Programming Interface
9.1 PCIe Compatibility
9.2 PCIe Register Map
9.2.1 Register Attributes
9.2.2 PCIe Configuration Space Summary
9.3 Mandatory PCI Configuration Registers
9.3.1 Vendor ID (0x0; RO)
9.3.2 Device ID (0x2; RO)
9.3.3 Command Register (0x4; R/W)
9.3.4 Status Register (0x6; RO)
9.3.5 Revision (0x8; RO)
9.3.6 Class Code (0x9; RO)
9.3.7 Cache Line Size (0xC; R/W)
9.3.8 Latency Timer (0xD; RO)
9.3.9 Header Type (0xE; RO)
9.3.10 BIST (0xF; RO)
9.3.11 Base Address Registers (0x10...0x27; R/W)
9.3.11.1 32-bit LAN BARs Mode Mapping
9.3.11.2 64-bit LAN BARs Mode Mapping
9.3.11.3 Base Address Register Fields
9.3.12 CardBus CIS (0x28; RO)
9.3.13 Subsystem Vendor ID (0x2C; RO)
9.3.14 Subsystem ID (0x2E; RO)
9.3.15 Expansion ROM Base Address (0x30; RW)
9.3.16 Cap_Ptr (0x34; RO)
9.3.17 Interrupt Line (0x3C; RW)
9.3.18 Interrupt Pin (0x3D; RO)
9.3.19 Max_Lat/Min_Gnt (0x3E; RO)
9.4 PCI Capabilities
9.4.1 PCI Power Management Capability
9.4.1.1 Capability ID (0x40; RO)
9.4.1.2 Next Pointer (0x41; RO)
9.4.1.3 Power Management Capabilities - PMC (0x42; RO)
9.4.1.4 Power Management Control / Status Register - PMCSR (0x44; R/W)
9.4.1.5 Bridge Support Extensions - PMCSR_BSE (0x46; RO)
9.4.1.6 Data Register (0x47; RO)
9.4.2 MSI Configuration
9.4.2.1 Capability ID (0x50; RO)
9.4.2.2 Next Pointer (0x51; RO)
9.4.2.3 Message Control (0x52; R/W)
9.4.2.4 Message Address Low (0x54; R/W)
9.4.2.5 Message Address High (0x58; R/W)
9.4.2.6 Message Data (0x5C; R/W)
9.4.2.7 Mask bits (0x60; R/W)
9.4.2.8 Pending Bits (0x64; R/W)
9.4.3 MSI-X Configuration
9.4.3.1 Capability ID (0x70; RO)
9.4.3.2 Next Pointer (0x71; RO)
9.4.3.3 Message Control (0x72; R/W)
9.4.3.4 MSI-X Table Offset (0x74; R/W)
9.4.3.5 MSI-X Pending Bit Array - PBA Offset (0x78; R/W)
9.4.3.6 MSI-X Interrupt Vector and Pending Bit Array Tables
9.4.3.6.1 MSI-X Table Entry Lower Address - MSIXTADD (BAR3: 0x0000 + 0x10n [n=0...4]; R/W)
9.4.3.6.2 MSI-X Table Entry Upper Address - MSIXTUADD (BAR3: 0x0004 + 0x10n [n=0...4]; R/W)
9.4.3.6.3 MSI-X Table Entry Message - MSIXTMSG (BAR3: 0x0008 + 0x10n [n=0...4]; R/ W)
9.4.3.6.4 MSI-X Table Entry Vector Control - MSIXTVCTRL (BAR3: 0x000C + 0x10n [n=0...4]; R/W)
9.4.3.6.5 MSIXPBA Bit Description – MSIXPBA (BAR3: 0x2000; RO)
9.4.4 Vital Product Data Registers
9.4.4.1 Capability ID (0xE0; RO)
9.4.4.2 Next Pointer (0xE1; RO)
9.4.4.3 VPD Address (0xE2; RW)
9.4.4.4 VPD Data (0xE4; RW)
9.4.5 PCIe Configuration Registers
9.4.5.1 Capability ID (0xA0; RO)
9.4.5.2 Next Pointer (0xA1; RO)
9.4.5.3 PCIe CAP (0xA2; RO)
9.4.5.4 Device Capabilities (0xA4; RO)
9.4.5.5 Device Control (0xA8; RW)
9.4.5.6 Device Status (0xAA; R/W1C)
9.4.5.7 Link Capabilities Register (0xAC; RO)
9.4.5.8 Link Control Register (0xB0; RO)
9.4.5.9 Link Status (0xB2; RO)
9.4.5.10 Reserved (0xB4-0xC0; RO)
9.4.5.11 Device Capabilities 2 (0xC4; RO)
9.4.5.12 Device Control 2 (0xC8; RW)
9.4.5.13 Link Control 2 (0xD0; RW)
9.4.5.14 Link Status 2 (0xD2; RO)
9.5 PCIe Extended Configuration Space
9.5.1 Advanced Error Reporting (AER) Capability
9.5.1.1 PCIe CAP ID (0x100; RO)
9.5.1.2 Uncorrectable Error Status (0x104; R/W1CS)
9.5.1.3 Uncorrectable Error Mask (0x108; RWS)
9.5.1.4 Uncorrectable Error Severity (0x10C; RWS)
9.5.1.5 Correctable Error Status (0x110; R/W1CS)
9.5.1.6 Correctable Error Mask (0x114; RWS)
9.5.1.7 Advanced Error Capabilities and Control Register (0x118; RWS)
9.5.1.8 Header Log (0x11C:0x128; RO)
9.5.2 Serial Number
9.5.2.1 Device Serial Number Enhanced Capability Header (0x140; RO)
9.5.2.2 Serial Number Register (0x144:0x148; RO)
9.5.3 Latency Tolerance Requirement Reporting (LTR) Capability
9.5.3.1 LTR CAP ID (0x1C0; RO)
9.5.3.2 LTR Capabilities (0x1C4; RW)
9.5.4 L1 Sub States Capability (offset - 0x1E0)
9.5.4.1 L1 Sub States Capability Header (0x1E0; RO)
9.5.4.2 L1 PM Sub States Capabilities Register (0x1E4; RW)
9.5.4.3 L1 PM Substates Control 1 Register (0x1E8; RW)
9.5.4.4 L1 PM Sub states Control 2 Register (0x1EC; RW)
9.5.5 Precision Time Measurements Capability - PTM (offset - 0x1F0)
9.5.5.1 PTM Capability Header (0x1F0; RO)
9.5.5.2 PTM Capability Register (0x1F4; RO)
9.5.5.3 PTM Control Register (0x1F8; RW)
10.0 System Manageability
10.1 Manageability Host Interface
10.1.1 Host Slave Command Interface - Event Flow
10.1.2 Host Interface Structure
10.1.3 Host Interface Commands
10.1.3.1 Get Firmware Version Host Command
10.1.3.2 Write Configuration Host Command
10.1.3.3 Read Configuration Host Command
10.1.3.4 Set PM Capabilities
10.1.3.5 Set Filter Indirect Table Select
10.1.3.6 Host Proxying Commands
10.1.3.6.1 Get Firmware Proxying Capabilities
10.1.3.6.2 Set Firmware Proxying Configuration
10.1.3.6.3 Set ARP Proxy Table Entry
10.1.3.6.4 Set NS (Neighbor Solicitation) Proxy Table Entry
10.1.3.6.5 Set mDNS Proxy
10.1.3.7 Imaging Wakeup Configuration Host Command
10.1.4 Host Isolate Support