Revision History
Preface
Summary Tables of Changes
Documentation Changes
1. Updates to Chapter 1, Volume 1
Chapter 1 About This Manual
1.1 Intel® 64 and IA-32 Processors Covered in this Manual
1.2 Overview of Volume 1: Basic Architecture
1.3 Notational Conventions
1.3.1 Bit and Byte Order
1.3.2 Reserved Bits and Software Compatibility
1.3.2.1 Instruction Operands
1.3.3 Hexadecimal and Binary Numbers
1.3.4 Segmented Addressing
1.3.5 A New Syntax for CPUID, CR, and MSR Values
1.3.6 Exceptions
1.4 Related Literature
2. Updates to Chapter 5, Volume 1
Chapter 5 Instruction Set Summary
5.1 General-Purpose Instructions
5.1.1 Data Transfer Instructions
5.1.2 Binary Arithmetic Instructions
5.1.3 Decimal Arithmetic Instructions
5.1.4 Logical Instructions
5.1.5 Shift and Rotate Instructions
5.1.6 Bit and Byte Instructions
5.1.7 Control Transfer Instructions
5.1.8 String Instructions
5.1.9 I/O Instructions
5.1.10 Enter and Leave Instructions
5.1.11 Flag Control (EFLAG) Instructions
5.1.12 Segment Register Instructions
5.1.13 Miscellaneous Instructions
5.1.14 User Mode Extended Sate Save/Restore Instructions
5.1.15 Random Number Generator Instructions
5.1.16 BMI1, BMI2
5.1.16.1 Detection of VEX-encoded GPR Instructions, LZCNT and TZCNT, PREFETCHW
5.2 x87 FPU Instructions
5.2.1 x87 FPU Data Transfer Instructions
5.2.2 x87 FPU Basic Arithmetic Instructions
5.2.3 x87 FPU Comparison Instructions
5.2.4 x87 FPU Transcendental Instructions
5.2.5 x87 FPU Load Constants Instructions
5.2.6 x87 FPU Control Instructions
5.3 x87 FPU AND SIMD State Management Instructions
5.4 MMX™ Instructions
5.4.1 MMX Data Transfer Instructions
5.4.2 MMX Conversion Instructions
5.4.3 MMX Packed Arithmetic Instructions
5.4.4 MMX Comparison Instructions
5.4.5 MMX Logical Instructions
5.4.6 MMX Shift and Rotate Instructions
5.4.7 MMX State Management Instructions
5.5 SSE Instructions
5.5.1 SSE SIMD Single-Precision Floating-Point Instructions
5.5.1.1 SSE Data Transfer Instructions
5.5.1.2 SSE Packed Arithmetic Instructions
5.5.1.3 SSE Comparison Instructions
5.5.1.4 SSE Logical Instructions
5.5.1.5 SSE Shuffle and Unpack Instructions
5.5.1.6 SSE Conversion Instructions
5.5.2 SSE MXCSR State Management Instructions
5.5.3 SSE 64-Bit SIMD Integer Instructions
5.5.4 SSE Cacheability Control, Prefetch, and Instruction Ordering Instructions
5.6 SSE2 Instructions
5.6.1 SSE2 Packed and Scalar Double-Precision Floating-Point Instructions
5.6.1.1 SSE2 Data Movement Instructions
5.6.1.2 SSE2 Packed Arithmetic Instructions
5.6.1.3 SSE2 Logical Instructions
5.6.1.4 SSE2 Compare Instructions
5.6.1.5 SSE2 Shuffle and Unpack Instructions
5.6.1.6 SSE2 Conversion Instructions
5.6.2 SSE2 Packed Single-Precision Floating-Point Instructions
5.6.3 SSE2 128-Bit SIMD Integer Instructions
5.6.4 SSE2 Cacheability Control and Ordering Instructions
5.7 SSE3 Instructions
5.7.1 SSE3 x87-FP Integer Conversion Instruction
5.7.2 SSE3 Specialized 128-bit Unaligned Data Load Instruction
5.7.3 SSE3 SIMD Floating-Point Packed ADD/SUB Instructions
5.7.4 SSE3 SIMD Floating-Point Horizontal ADD/SUB Instructions
5.7.5 SSE3 SIMD Floating-Point LOAD/MOVE/DUPLICATE Instructions
5.7.6 SSE3 Agent Synchronization Instructions
5.8 Supplemental Streaming SIMD Extensions 3 (SSSE3) Instructions
5.8.1 Horizontal Addition/Subtraction
5.8.2 Packed Absolute Values
5.8.3 Multiply and Add Packed Signed and Unsigned Bytes
5.8.4 Packed Multiply High with Round and Scale
5.8.5 Packed Shuffle Bytes
5.8.6 Packed Sign
5.8.7 Packed Align Right
5.9 SSE4 Instructions
5.10 SSE4.1 Instructions
5.10.1 Dword Multiply Instructions
5.10.2 Floating-Point Dot Product Instructions
5.10.3 Streaming Load Hint Instruction
5.10.4 Packed Blending Instructions
5.10.5 Packed Integer MIN/MAX Instructions
5.10.6 Floating-Point Round Instructions with Selectable Rounding Mode
5.10.7 Insertion and Extractions from XMM Registers
5.10.8 Packed Integer Format Conversions
5.10.9 Improved Sums of Absolute Differences (SAD) for 4-Byte Blocks
5.10.10 Horizontal Search
5.10.11 Packed Test
5.10.12 Packed Qword Equality Comparisons
5.10.13 Dword Packing With Unsigned Saturation
5.11 SSE4.2 Instruction Set
5.11.1 String and Text Processing Instructions
5.11.2 Packed Comparison SIMD integer Instruction
5.12 Intel® AES-NI and PCLMULQDQ
5.13 Intel® Advanced Vector Extensions (Intel® AVX)
5.14 16-bit Floating-Point Conversion
5.15 Fused-Multiply-ADD (FMA)
5.16 Intel® Advanced Vector Extensions 2 (Intel® AVX2)
5.17 Intel® Transactional Synchronization Extensions (Intel® TSX)
5.18 Intel® SHA Extensions
5.19 Intel® Advanced Vector Extensions 512 (Intel® AVX-512)
5.20 System Instructions
5.21 64-Bit Mode Instructions
5.22 Virtual-Machine Extensions
5.23 Safer Mode Extensions
5.24 Intel® Memory Protection Extensions
5.25 Intel® Software Guard Extensions
5.26 Shadow Stack Management Instructions
5.27 Control Transfer Terminating Instructions
3. Updates to Chapter 10, Volume 1
Chapter 10 Programming with Intel® Streaming SIMD Extensions (Intel® SSE)
10.1 Overview of SSE Extensions
10.2 SSE Programming Environment
10.2.1 SSE in 64-Bit Mode and Compatibility Mode
10.2.2 XMM Registers
10.2.3 MXCSR Control and Status Register
10.2.3.1 SIMD Floating-Point Mask and Flag Bits
10.2.3.2 SIMD Floating-Point Rounding Control Field
10.2.3.3 Flush-To-Zero
10.2.3.4 Denormals-Are-Zeros
10.2.4 Compatibility of SSE Extensions with SSE2/SSE3/MMX and the x87 FPU
10.3 SSE Data Types
10.4 SSE Instruction Set
10.4.1 SSE Packed and Scalar Floating-Point Instructions
10.4.1.1 SSE Data Movement Instructions
10.4.1.2 SSE Arithmetic Instructions
10.4.2 SSE Logical Instructions
10.4.2.1 SSE Comparison Instructions
10.4.2.2 SSE Shuffle and Unpack Instructions
10.4.3 SSE Conversion Instructions
10.4.4 SSE 64-Bit SIMD Integer Instructions
10.4.5 MXCSR State Management Instructions
10.4.6 Cacheability Control, Prefetch, and Memory Ordering Instructions
10.4.6.1 Cacheability Control Instructions
10.4.6.2 Caching of Temporal vs. Non-Temporal Data
10.4.6.3 PREFETCHh Instructions
10.4.6.4 SFENCE Instruction
10.5 FXSAVE and FXRSTOR Instructions
10.5.1 FXSAVE Area
10.5.1.1 x87 State
10.5.1.2 SSE State
10.5.2 Operation of FXSAVE
10.5.3 Operation of FXRSTOR
10.6 Handling SSE Instruction Exceptions
10.7 Writing Applications with the SSE Extensions
4. Updates to Chapter 15, Volume 1
Chapter 15 Programming with Intel® AVX-512
15.1 Overview
15.1.1 512-Bit Wide SIMD Register Support
15.1.2 32 SIMD Register Support
15.1.3 Eight Opmask Register Support
15.1.4 Instruction Syntax Enhancement
15.1.5 EVEX Instruction Encoding Support
15.2 Detection of AVX-512 Foundation Instructions
15.2.1 Additional 512-bit Instruction Extensions of the Intel AVX-512 Family
15.3 Detection of 512-bit Instruction Groups of Intel® AVX-512 Family
15.4 Detection of Intel AVX-512 Instruction Groups Operating at 256 and 128-bit Vector Lengths
15.5 Accessing XMM, YMM AND ZMM Registers
15.6 Enhanced Vector Programming Environment Using EVEX Encoding
15.6.1 OPMASK Register to Predicate Vector Data Processing
15.6.1.1 Opmask Register K0
15.6.1.2 Example of Opmask Usages
15.6.2 OpMask Instructions
15.6.3 Broadcast
15.6.4 Static Rounding Mode and Suppress All Exceptions
15.6.5 Compressed Disp8N Encoding
15.7 Memory Alignment
15.8 SIMD Floating-Point Exceptions
15.9 Instruction Exception Specification
15.10 Emulation
15.11 Writing floating-point exception handlers
5. Updates to Chapter 1, Volume 2A
Chapter 1 About This Manual
1.1 Intel® 64 and IA-32 Processors Covered in this Manual
1.2 Overview of Volume 2A, 2B, 2C and 2D: Instruction Set Reference
1.3 Notational Conventions
1.3.1 Bit and Byte Order
1.3.2 Reserved Bits and Software Compatibility
1.3.3 Instruction Operands
1.3.4 Hexadecimal and Binary Numbers
1.3.5 Segmented Addressing
1.3.6 Exceptions
1.3.7 A New Syntax for CPUID, CR, and MSR Values
1.4 Related Literature
6. Updates to Chapter 2, Volume 2A
Chapter 2 Instruction Format
2.1 Instruction Format for Protected Mode, real-address Mode, and virtual-8086 mode
2.1.1 Instruction Prefixes
2.1.2 Opcodes
2.1.3 ModR/M and SIB Bytes
2.1.4 Displacement and Immediate Bytes
2.1.5 Addressing-Mode Encoding of ModR/M and SIB Bytes
2.2 IA-32e Mode
2.2.1 REX Prefixes
2.2.1.1 Encoding
2.2.1.2 More on REX Prefix Fields
2.2.1.3 Displacement
2.2.1.4 Direct Memory-Offset MOVs
2.2.1.5 Immediates
2.2.1.6 RIP-Relative Addressing
2.2.1.7 Default 64-Bit Operand Size
2.2.2 Additional Encodings for Control and Debug Registers
2.3 Intel® Advanced Vector Extensions (Intel® AVX)
2.3.1 Instruction Format
2.3.2 VEX and the LOCK prefix
2.3.3 VEX and the 66H, F2H, and F3H prefixes
2.3.4 VEX and the REX prefix
2.3.5 The VEX Prefix
2.3.5.1 VEX Byte 0, bits[7:0]
2.3.5.2 VEX Byte 1, bit [7] - ‘R’
2.3.5.3 3-byte VEX byte 1, bit[6] - ‘X’
2.3.5.4 3-byte VEX byte 1, bit[5] - ‘B’
2.3.5.5 3-byte VEX byte 2, bit[7] - ‘W’
2.3.5.6 2-byte VEX Byte 1, bits[6:3] and 3-byte VEX Byte 2, bits [6:3]- ‘vvvv’ the Source or Dest Register Specifier
2.3.6 Instruction Operand Encoding and VEX.vvvv, ModR/M
2.3.6.1 3-byte VEX byte 1, bits[4:0] - “m-mmmm”
2.3.6.2 2-byte VEX byte 1, bit[2], and 3-byte VEX byte 2, bit [2]- “L”
2.3.6.3 2-byte VEX byte 1, bits[1:0], and 3-byte VEX byte 2, bits [1:0]- “pp”
2.3.7 The Opcode Byte
2.3.8 The MODRM, SIB, and Displacement Bytes
2.3.9 The Third Source Operand (Immediate Byte)
2.3.10 AVX Instructions and the Upper 128-bits of YMM registers
2.3.10.1 Vector Length Transition and Programming Considerations
2.3.11 AVX Instruction Length
2.3.12 Vector SIB (VSIB) Memory Addressing
2.3.12.1 64-bit Mode VSIB Memory Addressing
2.4 AVX and SSE Instruction Exception Specification
2.4.1 Exceptions Type 1 (Aligned memory reference)
2.4.2 Exceptions Type 2 (>=16 Byte Memory Reference, Unaligned)
2.4.3 Exceptions Type 3 (<16 Byte memory argument)
2.4.4 Exceptions Type 4 (>=16 Byte mem arg, no alignment, no floating-point exceptions)
2.4.5 Exceptions Type 5 (<16 Byte mem arg and no FP exceptions)
2.4.6 Exceptions Type 6 (VEX-Encoded Instructions Without Legacy SSE Analogues)
2.4.7 Exceptions Type 7 (No FP exceptions, no memory arg)
2.4.8 Exceptions Type 8 (AVX and no memory argument)
2.4.9 Exceptions Type 11 (VEX-only, mem arg no AC, floating-point exceptions)
2.4.10 Exceptions Type 12 (VEX-only, VSIB mem arg, no AC, no floating-point exceptions)
2.5 VEX Encoding Support for GPR Instructions
2.5.1 Exceptions Type 13 (VEX-Encoded GPR Instructions)
2.6 Intel® AVX-512 Encoding
2.6.1 Instruction Format and EVEX
2.6.2 Register Specifier Encoding and EVEX
2.6.3 Opmask Register Encoding
2.6.4 Masking Support in EVEX
2.6.5 Compressed Displacement (disp8N) Support in EVEX
2.6.6 EVEX Encoding of Broadcast/Rounding/SAE Support
2.6.7 Embedded Broadcast Support in EVEX
2.6.8 Static Rounding Support in EVEX
2.6.9 SAE Support in EVEX
2.6.10 Vector Length Orthogonality
2.6.11 #UD Equations for EVEX
2.6.11.1 State Dependent #UD
2.6.11.2 Opcode Independent #UD
2.6.11.3 Opcode Dependent #UD
2.6.12 Device Not Available
2.6.13 Scalar Instructions
2.7 Exception Classifications of EVEX-Encoded instructions
2.7.1 Exceptions Type E1 and E1NF of EVEX-Encoded Instructions
2.7.2 Exceptions Type E2 of EVEX-Encoded Instructions
2.7.3 Exceptions Type E3 and E3NF of EVEX-Encoded Instructions
2.7.4 Exceptions Type E4 and E4NF of EVEX-Encoded Instructions
2.7.5 Exceptions Type E5 and E5NF
2.7.6 Exceptions Type E6 and E6NF
2.7.7 Exceptions Type E7NM
2.7.8 Exceptions Type E9 and E9NF
2.7.9 Exceptions Type E10 and E10NF
2.7.10 Exception Type E11 (EVEX-only, mem arg no AC, floating-point exceptions)
2.7.11 Exception Type E12 and E12NP (VSIB mem arg, no AC, no floating-point exceptions)
2.8 Exception Classifications of Opmask instructions
7. Updates to Chapter 3, Volume 2A
INSTRUCTION SET REFERENCE, A-L
AESDEC
AESDECLAST
AESENC
AESENCLAST
CALL
CMPSS
CPUID
FRSTOR
GF2P8AFFINEINVQB
GF2P8AFFINEQB
GF2P8MULB
IRET/IRETD/IRETQ
LZCNT
8. Updates to Chapter 4, Volume 2B
PCLMULQDQ
PSIGNB/PSIGNW/PSIGND
PSLLW/PSLLD/PSLLQ
PSRLW/PSRLD/PSRLQ
PTEST
RDPMC
SLDT
STOS/STOSB/STOSW/STOSD/STOSQ
TZCNT
9. Updates to Chapter 5, Volume 2C
VCVTNE2PS2BF16
VCVTNEPS2BF16
VDBPSADBW
VDPBF16PS
VFIXUPIMMPD
VFIXUPIMMPS
VFMADD132PD/VFMADD213PD/VFMADD231PD
VP2INTERSECTD/VP2INTERSECTQ
VPERMD/VPERMW
VPTESTNMB/W/D/Q
VTESTPD/VTESTPS
WBNOINVD
10. Updates to Chapter 6, Volume 2D
GETSEC[ENTERACCS]
11. Updates to Chapter 7, Volume 2D
PREFETCHWT1
12. Updates to Chapter 1, Volume 3A
Chapter 1 About This Manual
1.1 Intel® 64 and IA-32 Processors Covered in this Manual
1.2 Overview of The SYSTEM PROGRAMMING GUIDE
1.3 Notational Conventions
1.3.1 Bit and Byte Order
1.3.2 Reserved Bits and Software Compatibility
1.3.3 Instruction Operands
1.3.4 Hexadecimal and Binary Numbers
1.3.5 Segmented Addressing
1.3.6 Syntax for CPUID, CR, and MSR Values
1.3.7 Exceptions
1.4 Related Literature
13. Updates to Chapter 4, Volume 3A
Chapter 4 Paging
4.1 Paging Modes and Control Bits
4.1.1 Four Paging Modes
4.1.2 Paging-Mode Enabling
4.1.3 Paging-Mode Modifiers
4.1.4 Enumeration of Paging Features by CPUID
4.2 Hierarchical Paging Structures: an Overview
4.3 32-Bit Paging
4.4 PAE Paging
4.4.1 PDPTE Registers
4.4.2 Linear-Address Translation with PAE Paging
4.5 4-Level Paging and 5-Level Paging
4.6 Access Rights
4.6.1 Determination of Access Rights
4.6.2 Protection Keys
4.7 Page-Fault Exceptions
4.8 Accessed and Dirty Flags
4.9 Paging and Memory Typing
4.9.1 Paging and Memory Typing When the PAT is Not Supported (Pentium Pro and Pentium II Processors)
4.9.2 Paging and Memory Typing When the PAT is Supported (Pentium III and More Recent Processor Families)
4.9.3 Caching Paging-Related Information about Memory Typing
4.10 Caching Translation Information
4.10.1 Process-Context Identifiers (PCIDs)
4.10.2 Translation Lookaside Buffers (TLBs)
4.10.2.1 Page Numbers, Page Frames, and Page Offsets
4.10.2.2 Caching Translations in TLBs
4.10.2.3 Details of TLB Use
4.10.2.4 Global Pages
4.10.3 Paging-Structure Caches
4.10.3.1 Caches for Paging Structures
4.10.3.2 Using the Paging-Structure Caches to Translate Linear Addresses
4.10.3.3 Multiple Cached Entries for a Single Paging-Structure Entry
4.10.4 Invalidation of TLBs and Paging-Structure Caches
4.10.4.1 Operations that Invalidate TLBs and Paging-Structure Caches
4.10.4.2 Recommended Invalidation
4.10.4.3 Optional Invalidation
4.10.4.4 Delayed Invalidation
4.10.5 Propagation of Paging-Structure Changes to Multiple Processors
4.11 Interactions with Virtual-Machine Extensions (VMX)
4.11.1 VMX Transitions
4.11.2 VMX Support for Address Translation
4.12 Using Paging for Virtual Memory
4.13 Mapping Segments to Pages
14. Updates to Chapter 6, Volume 3A
Chapter 6 Interrupt and Exception Handling
6.1 Interrupt and Exception Overview
6.2 Exception and Interrupt Vectors
6.3 Sources of Interrupts
6.3.1 External Interrupts
6.3.2 Maskable Hardware Interrupts
6.3.3 Software-Generated Interrupts
6.4 Sources of Exceptions
6.4.1 Program-Error Exceptions
6.4.2 Software-Generated Exceptions
6.4.3 Machine-Check Exceptions
6.5 Exception Classifications
6.6 Program or Task Restart
6.7 NonMaskable Interrupt (NMI)
6.7.1 Handling Multiple NMIs
6.8 Enabling and Disabling Interrupts
6.8.1 Masking Maskable Hardware Interrupts
6.8.2 Masking Instruction Breakpoints
6.8.3 Masking Exceptions and Interrupts When Switching Stacks
6.9 Priority Among Simultaneous Exceptions and Interrupts
6.10 Interrupt Descriptor Table (IDT)
6.11 IDT Descriptors
6.12 Exception and Interrupt Handling
6.12.1 Exception- or Interrupt-Handler Procedures
6.12.1.1 Shadow Stack Usage on Transfers to Interrupt and Exception Handling Routines
6.12.1.2 Protection of Exception- and Interrupt-Handler Procedures
6.12.1.3 Flag Usage By Exception- or Interrupt-Handler Procedure
6.12.2 Interrupt Tasks
6.13 Error Code
6.14 Exception and Interrupt Handling in 64-bit Mode
6.14.1 64-Bit Mode IDT
6.14.2 64-Bit Mode Stack Frame
6.14.3 IRET in IA-32e Mode
6.14.4 Stack Switching in IA-32e Mode
6.14.5 Interrupt Stack Table
6.15 Exception and Interrupt Reference
Interrupt 0—Divide Error Exception (#DE)
Interrupt 1—Debug Exception (#DB)
Interrupt 2—NMI Interrupt
Interrupt 3—Breakpoint Exception (#BP)
Interrupt 4—Overflow Exception (#OF)
Interrupt 5—BOUND Range Exceeded Exception (#BR)
Interrupt 6—Invalid Opcode Exception (#UD)
Interrupt 7—Device Not Available Exception (#NM)
Interrupt 8—Double Fault Exception (#DF)
Interrupt 9—Coprocessor Segment Overrun
Interrupt 10—Invalid TSS Exception (#TS)
Interrupt 11—Segment Not Present (#NP)
Interrupt 12—Stack Fault Exception (#SS)
Interrupt 13—General Protection Exception (#GP)
Interrupt 14—Page-Fault Exception (#PF)
Interrupt 16—x87 FPU Floating-Point Error (#MF)
Interrupt 17—Alignment Check Exception (#AC)
Interrupt 18—Machine-Check Exception (#MC)
Interrupt 19—SIMD Floating-Point Exception (#XM)
Interrupt 20—Virtualization Exception (#VE)
Interrupt 21—Control Protection Exception (#CP)
Interrupts 32 to 255—User Defined Interrupts
15. Updates to Chapter 7, Volume 3A
Chapter 7 Task Management
7.1 Task Management Overview
7.1.1 Task Structure
7.1.2 Task State
7.1.3 Executing a Task
7.2 Task Management Data Structures
7.2.1 Task-State Segment (TSS)
7.2.2 TSS Descriptor
7.2.3 TSS Descriptor in 64-bit mode
7.2.4 Task Register
7.2.5 Task-Gate Descriptor
7.3 Task Switching
7.4 Task Linking
7.4.1 Use of Busy Flag To Prevent Recursive Task Switching
7.4.2 Modifying Task Linkages
7.5 Task Address Space
7.5.1 Mapping Tasks to the Linear and Physical Address Spaces
7.5.2 Task Logical Address Space
7.6 16-Bit Task-State Segment (TSS)
7.7 Task Management in 64-bit Mode
16. Updates to Chapter 10, Volume 3A
Chapter 10 Advanced Programmable Interrupt Controller (APIC)
10.1 Local and I/O APIC Overview
10.2 System Bus Vs. APIC Bus
10.3 The Intel® 82489DX External APIC, the APIC, the xAPIC, and the X2APIC
10.4 Local APIC
10.4.1 The Local APIC Block Diagram
10.4.2 Presence of the Local APIC
10.4.3 Enabling or Disabling the Local APIC
10.4.4 Local APIC Status and Location
10.4.5 Relocating the Local APIC Registers
10.4.6 Local APIC ID
10.4.7 Local APIC State
10.4.7.1 Local APIC State After Power-Up or Reset
10.4.7.2 Local APIC State After It Has Been Software Disabled
10.4.7.3 Local APIC State After an INIT Reset (“Wait-for-SIPI” State)
10.4.7.4 Local APIC State After It Receives an INIT-Deassert IPI
10.4.8 Local APIC Version Register
10.5 Handling Local Interrupts
10.5.1 Local Vector Table
10.5.2 Valid Interrupt Vectors
10.5.3 Error Handling
10.5.4 APIC Timer
10.5.4.1 TSC-Deadline Mode
10.5.5 Local Interrupt Acceptance
10.6 Issuing Interprocessor Interrupts
10.6.1 Interrupt Command Register (ICR)
10.6.2 Determining IPI Destination
10.6.2.1 Physical Destination Mode
10.6.2.2 Logical Destination Mode
10.6.2.3 Broadcast/Self Delivery Mode
10.6.2.4 Lowest Priority Delivery Mode
10.6.3 IPI Delivery and Acceptance
10.7 System and APIC Bus Arbitration
10.8 Handling Interrupts
10.8.1 Interrupt Handling with the Pentium 4 and Intel Xeon Processors
10.8.2 Interrupt Handling with the P6 Family and Pentium Processors
10.8.3 Interrupt, Task, and Processor Priority
10.8.3.1 Task and Processor Priorities
10.8.4 Interrupt Acceptance for Fixed Interrupts
10.8.5 Signaling Interrupt Servicing Completion
10.8.6 Task Priority in IA-32e Mode
10.8.6.1 Interaction of Task Priorities between CR8 and APIC
10.9 Spurious Interrupt
10.10 APIC Bus Message Passing Mechanism and Protocol (P6 Family, Pentium Processors)
10.10.1 Bus Message Formats
10.11 Message Signalled Interrupts
10.11.1 Message Address Register Format
10.11.2 Message Data Register Format
10.12 Extended XAPIC (x2APIC)
10.12.1 Detecting and Enabling x2APIC Mode
10.12.1.1 Instructions to Access APIC Registers
10.12.1.2 x2APIC Register Address Space
10.12.1.3 Reserved Bit Checking
10.12.2 x2APIC Register Availability
10.12.3 MSR Access in x2APIC Mode
10.12.4 VM-Exit Controls for MSRs and x2APIC Registers
10.12.5 x2APIC State Transitions
10.12.5.1 x2APIC States
x2APIC After Reset
x2APIC Transitions From x2APIC Mode
x2APIC Transitions From Disabled Mode
State Changes From xAPIC Mode to x2APIC Mode
10.12.6 Routing of Device Interrupts in x2APIC Mode
10.12.7 Initialization by System Software
10.12.8 CPUID Extensions And Topology Enumeration
10.12.8.1 Consistency of APIC IDs and CPUID
10.12.9 ICR Operation in x2APIC Mode
10.12.10 Determining IPI Destination in x2APIC Mode
10.12.10.1 Logical Destination Mode in x2APIC Mode
10.12.10.2 Deriving Logical x2APIC ID from the Local x2APIC ID
10.12.11 SELF IPI Register
10.13 APIC Bus Message Formats
10.13.1 Bus Message Formats
10.13.2 EOI Message
10.13.2.1 Short Message
10.13.2.2 Non-focused Lowest Priority Message
10.13.2.3 APIC Bus Status Cycles
17. Updates to Chapter 11, Volume 3A
Chapter 11 Memory Cache Control
11.1 Internal Caches, TLBs, and Buffers
11.2 Caching Terminology
11.3 Methods of Caching Available
11.3.1 Buffering of Write Combining Memory Locations
11.3.2 Choosing a Memory Type
11.3.3 Code Fetches in Uncacheable Memory
11.4 Cache Control Protocol
11.5 Cache Control
11.5.1 Cache Control Registers and Bits
11.5.2 Precedence of Cache Controls
11.5.2.1 Selecting Memory Types for Pentium Pro and Pentium II Processors
11.5.2.2 Selecting Memory Types for Pentium III and More Recent Processor Families
11.5.2.3 Writing Values Across Pages with Different Memory Types
11.5.3 Preventing Caching
11.5.4 Disabling and Enabling the L3 Cache
11.5.5 Cache Management Instructions
11.5.6 L1 Data Cache Context Mode
11.5.6.1 Adaptive Mode
11.5.6.2 Shared Mode
11.6 Self-Modifying Code
11.7 Implicit Caching (Pentium 4, Intel Xeon, and P6 Family Processors)
11.8 Explicit Caching
11.9 Invalidating the Translation Lookaside Buffers (TLBs)
11.10 Store Buffer
11.11 Memory Type Range Registers (MTRRs)
11.11.1 MTRR Feature Identification
11.11.2 Setting Memory Ranges with MTRRs
11.11.2.1 IA32_MTRR_DEF_TYPE MSR
11.11.2.2 Fixed Range MTRRs
11.11.2.3 Variable Range MTRRs
11.11.2.4 System-Management Range Register Interface
11.11.3 Example Base and Mask Calculations
11.11.3.1 Base and Mask Calculations for Greater-Than 36-bit Physical Address Support
11.11.4 Range Size and Alignment Requirement
11.11.4.1 MTRR Precedences
11.11.5 MTRR Initialization
11.11.6 Remapping Memory Types
11.11.7 MTRR Maintenance Programming Interface
11.11.7.1 MemTypeGet() Function
11.11.7.2 MemTypeSet() Function
11.11.8 MTRR Considerations in MP Systems
11.11.9 Large Page Size Considerations
11.12 Page Attribute Table (PAT)
11.12.1 Detecting Support for the PAT Feature
11.12.2 IA32_PAT MSR
11.12.3 Selecting a Memory Type from the PAT
11.12.4 Programming the PAT
11.12.5 PAT Compatibility with Earlier IA-32 Processors
18. Updates to Chapter 17, Volume 3B
Chapter 17 Debug, Branch Profile, TSC, and Intel® Resource Director Technology (Intel® RDT) Features
17.1 Overview of Debug Support Facilities
17.2 Debug Registers
17.2.1 Debug Address Registers (DR0-DR3)
17.2.2 Debug Registers DR4 and DR5
17.2.3 Debug Status Register (DR6)
17.2.4 Debug Control Register (DR7)
17.2.5 Breakpoint Field Recognition
17.2.6 Debug Registers and Intel® 64 Processors
17.3 Debug Exceptions
17.3.1 Debug Exception (#DB)—Interrupt Vector 1
17.3.1.1 Instruction-Breakpoint Exception Condition
17.3.1.2 Data Memory and I/O Breakpoint Exception Conditions
17.3.1.3 General-Detect Exception Condition
17.3.1.4 Single-Step Exception Condition
17.3.1.5 Task-Switch Exception Condition
17.3.2 Breakpoint Exception (#BP)—Interrupt Vector 3
17.3.3 Debug Exceptions, Breakpoint Exceptions, and Restricted Transactional Memory (RTM)
17.4 Last Branch, Interrupt, and Exception Recording Overview
17.4.1 IA32_DEBUGCTL MSR
17.4.2 Monitoring Branches, Exceptions, and Interrupts
17.4.3 Single-Stepping on Branches
17.4.4 Branch Trace Messages
17.4.4.1 Branch Trace Message Visibility
17.4.5 Branch Trace Store (BTS)
17.4.6 CPL-Qualified Branch Trace Mechanism
17.4.7 Freezing LBR and Performance Counters on PMI
17.4.8 LBR Stack
17.4.8.1 LBR Stack and Intel® 64 Processors
17.4.8.2 LBR Stack and IA-32 Processors
17.4.8.3 Last Exception Records and Intel 64 Architecture
17.4.9 BTS and DS Save Area
17.4.9.1 64 Bit Format of the DS Save Area
17.4.9.2 Setting Up the DS Save Area
17.4.9.3 Setting Up the BTS Buffer
17.4.9.4 Setting Up CPL-Qualified BTS
17.4.9.5 Writing the DS Interrupt Service Routine
17.5 Last Branch, Interrupt, and Exception Recording (Intel® Core™ 2 Duo and Intel® Atom™ Processors)
17.5.1 LBR Stack
17.5.2 LBR Stack in Intel Atom Processors based on the Silvermont Microarchitecture
17.6 Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Goldmont Microarchitecture
17.7 Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Goldmont Plus Microarchitecture
17.8 Last Branch, Interrupt and Exception Recording for Intel® Xeon Phi™ Processor 7200/5200/3200
17.9 Last Branch, Interrupt, and Exception Recording for Processors based on Intel® Microarchitecture code name Nehalem
17.9.1 LBR Stack
17.9.2 Filtering of Last Branch Records
17.10 Last Branch, Interrupt, and Exception Recording for Processors based on Intel® Microarchitecture code name Sandy Bridge
17.11 Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Haswell Microarchitecture
17.11.1 LBR Stack Enhancement
17.12 Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Skylake Microarchitecture
17.12.1 MSR_LBR_INFO_x MSR
17.12.2 Streamlined Freeze_LBRs_On_PMI Operation
17.12.3 LBR Behavior and Deep C-State
17.13 Last Branch, Interrupt, and Exception Recording (Processors based on Intel NetBurst® Microarchitecture)
17.13.1 MSR_DEBUGCTLA MSR
17.13.2 LBR Stack for Processors Based on Intel NetBurst® Microarchitecture
17.13.3 Last Exception Records
17.14 Last Branch, Interrupt, and Exception Recording (Intel® Core™ Solo and Intel® Core™ Duo Processors)
17.15 Last Branch, Interrupt, and Exception Recording (Pentium M Processors)
17.16 Last Branch, Interrupt, and Exception Recording (P6 Family Processors)
17.16.1 DEBUGCTLMSR Register
17.16.2 Last Branch and Last Exception MSRs
17.16.3 Monitoring Branches, Exceptions, and Interrupts
17.17 Time-Stamp Counter
17.17.1 Invariant TSC
17.17.2 IA32_TSC_AUX Register and RDTSCP Support
17.17.3 Time-Stamp Counter Adjustment
17.17.4 Invariant Time-Keeping
17.18 Intel® Resource Director Technology (Intel® RDT) Monitoring Features
17.18.1 Overview of Cache Monitoring Technology and Memory Bandwidth Monitoring
17.18.2 Enabling Monitoring: Usage Flow
17.18.3 Enumeration and Detecting Support of Cache Monitoring Technology and Memory Bandwidth Monitoring
17.18.4 Monitoring Resource Type and Capability Enumeration
17.18.5 Feature-Specific Enumeration
17.18.5.1 Cache Monitoring Technology
17.18.5.2 Memory Bandwidth Monitoring
17.18.6 Monitoring Resource RMID Association
17.18.7 Monitoring Resource Selection and Reporting Infrastructure
17.18.8 Monitoring Programming Considerations
17.18.8.1 Monitoring Dynamic Configuration
17.18.8.2 Monitoring Operation With Power Saving Features
17.18.8.3 Monitoring Operation with Other Operating Modes
17.18.8.4 Monitoring Operation with RAS Features
17.19 Intel® Resource Director Technology (Intel® RDT) Allocation Features
17.19.1 Introduction to Cache Allocation Technology (CAT)
17.19.2 Cache Allocation Technology Architecture
17.19.3 Code and Data Prioritization (CDP) Technology
17.19.4 Enabling Cache Allocation Technology Usage Flow
17.19.4.1 Enumeration and Detection Support of Cache Allocation Technology
17.19.4.2 Cache Allocation Technology: Resource Type and Capability Enumeration
17.19.4.3 Cache Allocation Technology: Cache Mask Configuration
17.19.4.4 Class of Service to Cache Mask Association: Common Across Allocation Features
17.19.5 Code and Data Prioritization (CDP): Enumerating and Enabling L3 CDP Technology
17.19.5.1 Mapping Between L3 CDP Masks and CAT Masks
17.19.6 Code and Data Prioritization (CDP): Enumerating and Enabling L2 CDP Technology
17.19.6.1 Mapping Between L2 CDP Masks and L2 CAT Masks
17.19.6.2 Common L2 and L3 CDP Programming Considerations
17.19.6.3 Cache Allocation Technology Dynamic Configuration
17.19.6.4 Cache Allocation Technology Operation With Power Saving Features
17.19.6.5 Cache Allocation Technology Operation with Other Operating Modes
17.19.6.6 Associating Threads with CAT/CDP Classes of Service
17.19.7 Introduction to Memory Bandwidth Allocation
17.19.7.1 Memory Bandwidth Allocation Enumeration
17.19.7.2 Memory Bandwidth Allocation Configuration
17.19.7.3 Memory Bandwidth Allocation Usage Considerations
19. Updates to Chapter 18, Volume 3B
Chapter 18 Performance Monitoring
18.1 Performance Monitoring Overview
18.2 Architectural Performance Monitoring
18.2.1 Architectural Performance Monitoring Version 1
18.2.1.1 Architectural Performance Monitoring Version 1 Facilities
18.2.1.2 Pre-defined Architectural Performance Events
18.2.2 Architectural Performance Monitoring Version 2
18.2.3 Architectural Performance Monitoring Version 3
18.2.3.1 AnyThread Counting and Software Evolution
18.2.4 Architectural Performance Monitoring Version 4
18.2.4.1 Enhancement in IA32_PERF_GLOBAL_STATUS
18.2.4.2 IA32_PERF_GLOBAL_STATUS_RESET and IA32_PERF_GLOBAL_STATUS_SET MSRS
18.2.4.3 IA32_PERF_GLOBAL_INUSE MSR
18.2.5 Architectural Performance Monitoring Version 5
18.2.5.1 AnyThread Mode Deprecation
18.2.5.2 Fixed Counter Enumeration
18.2.6 Full-Width Writes to Performance Counter Registers
18.3 Performance Monitoring (Intel® Core™ Processors and Intel® Xeon® Processors)
18.3.1 Performance Monitoring for Processors Based on Intel® Microarchitecture Code Name Nehalem
18.3.1.1 Enhancements of Performance Monitoring in the Processor Core
18.3.1.2 Performance Monitoring Facility in the Uncore
18.3.1.3 Intel® Xeon® Processor 7500 Series Performance Monitoring Facility
18.3.2 Performance Monitoring for Processors Based on Intel® Microarchitecture Code Name Westmere
18.3.3 Intel® Xeon® Processor E7 Family Performance Monitoring Facility
18.3.4 Performance Monitoring for Processors Based on Intel® Microarchitecture Code Name Sandy Bridge
18.3.4.1 Global Counter Control Facilities In Intel® Microarchitecture Code Name Sandy Bridge
18.3.4.2 Counter Coalescence
18.3.4.3 Full Width Writes to Performance Counters
18.3.4.4 PEBS Support in Intel® Microarchitecture Code Name Sandy Bridge
18.3.4.5 Off-core Response Performance Monitoring
18.3.4.6 Uncore Performance Monitoring Facilities In Intel® Core™ i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series
18.3.4.7 Intel® Xeon® Processor E5 Family Performance Monitoring Facility
18.3.4.8 Intel® Xeon® Processor E5 Family Uncore Performance Monitoring Facility
18.3.5 3rd Generation Intel® Core™ Processor Performance Monitoring Facility
18.3.5.1 Intel® Xeon® Processor E5 v2 and E7 v2 Family Uncore Performance Monitoring Facility
18.3.6 4th Generation Intel® Core™ Processor Performance Monitoring Facility
18.3.6.1 Processor Event Based Sampling (PEBS) Facility
18.3.6.2 PEBS Data Format
18.3.6.3 PEBS Data Address Profiling
18.3.6.4 Off-core Response Performance Monitoring
18.3.6.5 Performance Monitoring and Intel® TSX
18.3.6.6 Uncore Performance Monitoring Facilities in the 4th Generation Intel® Core™ Processors
18.3.6.7 Intel® Xeon® Processor E5 v3 Family Uncore Performance Monitoring Facility
18.3.7 5th Generation Intel® Core™ Processor and Intel® Core™ M Processor Performance Monitoring Facility
18.3.8 6th Generation, 7th Generation and 8th Generation Intel® Core™ Processor Performance Monitoring Facility
18.3.8.1 Processor Event Based Sampling (PEBS) Facility
18.3.8.2 Off-core Response Performance Monitoring
18.3.8.3 Uncore Performance Monitoring Facilities on Intel® Core™ Processors Based on Cannon Lake Microarchitecture
18.3.9 10th Generation Intel® Core™ Processor Performance Monitoring Facility
18.3.9.1 Processor Event Based Sampling (PEBS) Facility
18.3.9.2 Off-core Response Performance Monitoring
18.3.9.3 Performance Metrics
18.4 Performance monitoring (Intel® Xeon™ Phi Processors)
18.4.1 Intel® Xeon Phi™ Processor 7200/5200/3200 Performance Monitoring
18.4.1.1 Enhancements of Performance Monitoring in the Intel® Xeon Phi™ processor Tile
18.5 Performance Monitoring (Intel Atom® Processors)
18.5.1 Performance Monitoring (45 nm and 32 nm Intel Atom® Processors)
18.5.2 Performance Monitoring for Silvermont Microarchitecture
18.5.2.1 Enhancements of Performance Monitoring in the Processor Core
18.5.2.2 Offcore Response Event
18.5.2.3 Average Offcore Request Latency Measurement
18.5.3 Performance Monitoring for Goldmont Microarchitecture
18.5.3.1 Processor Event Based Sampling (PEBS)
18.5.3.2 Offcore Response Event
18.5.3.3 Average Offcore Request Latency Measurement
18.5.4 Performance Monitoring for Goldmont Plus Microarchitecture
18.5.4.1 Extended PEBS
18.5.5 Performance Monitoring for Tremont Microarchitecture
18.5.5.1 Adaptive PEBS
18.5.5.2 PEBS output to Intel® Processor Trace
18.5.5.3 Precise Distribution Support on Fixed Counter 0
18.5.5.4 Compatibility Enhancements to Offcore Response MSRs
18.6 Performance Monitoring (Legacy Intel Processors)
18.6.1 Performance Monitoring (Intel® Core™ Solo and Intel® Core™ Duo Processors)
18.6.2 Performance Monitoring (Processors Based on Intel® Core™ Microarchitecture)
18.6.2.1 Fixed-function Performance Counters
18.6.2.2 Global Counter Control Facilities
18.6.2.3 At-Retirement Events
18.6.2.4 Processor Event Based Sampling (PEBS)
18.6.3 Performance Monitoring (Processors Based on Intel NetBurst® Microarchitecture)
18.6.3.1 ESCR MSRs
18.6.3.2 Performance Counters
18.6.3.3 CCCR MSRs
18.6.3.4 Debug Store (DS) Mechanism
18.6.3.5 Programming the Performance Counters for Non-Retirement Events
18.6.3.6 At-Retirement Counting
18.6.3.7 Tagging Mechanism for Replay_event
18.6.3.8 Processor Event-Based Sampling (PEBS)
18.6.3.9 Operating System Implications
18.6.4 Performance Monitoring and Intel Hyper-Threading Technology in Processors Based on Intel NetBurst® Microarchitecture
18.6.4.1 ESCR MSRs
18.6.4.2 CCCR MSRs
18.6.4.3 IA32_PEBS_ENABLE MSR
18.6.4.4 Performance Monitoring Events
18.6.4.5 Counting Clocks on systems with Intel Hyper-Threading Technology in Processors Based on Intel NetBurst® Microarchitecture
18.6.5 Performance Monitoring and Dual-Core Technology
18.6.6 Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache
18.6.7 Performance Monitoring on L3 and Caching Bus Controller Sub-Systems
18.6.7.1 Overview of Performance Monitoring with L3/Caching Bus Controller
18.6.7.2 GBSQ Event Interface
18.6.7.3 GSNPQ Event Interface
18.6.7.4 FSB Event Interface
18.6.7.5 Common Event Control Interface
18.6.8 Performance Monitoring (P6 Family Processor)
18.6.8.1 PerfEvtSel0 and PerfEvtSel1 MSRs
18.6.8.2 PerfCtr0 and PerfCtr1 MSRs
18.6.8.3 Starting and Stopping the Performance-Monitoring Counters
18.6.8.4 Event and Time-Stamp Monitoring Software
18.6.8.5 Monitoring Counter Overflow
18.6.9 Performance Monitoring (Pentium Processors)
18.6.9.1 Control and Event Select Register (CESR)
18.6.9.2 Use of the Performance-Monitoring Pins
18.6.9.3 Events Counted
18.7 Counting Clocks
18.7.1 Non-Halted Reference Clockticks
18.7.2 Cycle Counting and Opportunistic Processor Operation
18.7.3 Determining the Processor Base Frequency
18.7.3.1 For Intel® Processors Based on Microarchitecture Code Name Sandy Bridge, Ivy Bridge, Haswell and Broadwell
18.7.3.2 For Intel® Processors Based on Microarchitecture Code Name Nehalem
18.7.3.3 For Intel® Atom™ Processors Based on the Silvermont Microarchitecture (Including Intel Processors Based on Airmont Microarchitecture)
18.7.3.4 For Intel® Core™ 2 Processor Family and for Intel® Xeon® Processors Based on Intel Core Microarchitecture
18.8 IA32_PERF_CAPABILITIES MSR Enumeration
18.8.1 Filtering of SMM Handler Overhead
18.9 PEBS Facility
18.9.1 Extended PEBS
18.9.2 Adaptive PEBS
18.9.2.1 Adaptive_Record Counter Control
18.9.2.2 PEBS Record Format
18.9.2.3 MSR_PEBS_DATA_CFG
18.9.2.4 PEBS Record Examples
18.9.3 Precise Distribution of Instructions Retired (PDIR) Facility
18.9.4 Reduced Skid PEBS
20. Updates to Chapter 24, Volume 3B
Chapter 24 Virtual Machine Control Structures
24.1 Overview
24.2 Format of the VMCS Region
24.3 Organization of VMCS Data
24.4 Guest-State Area
24.4.1 Guest Register State
24.4.2 Guest Non-Register State
24.5 Host-State Area
24.6 VM-Execution Control Fields
24.6.1 Pin-Based VM-Execution Controls
24.6.2 Processor-Based VM-Execution Controls
24.6.3 Exception Bitmap
24.6.4 I/O-Bitmap Addresses
24.6.5 Time-Stamp Counter Offset and Multiplier
24.6.6 Guest/Host Masks and Read Shadows for CR0 and CR4
24.6.7 CR3-Target Controls
24.6.8 Controls for APIC Virtualization
24.6.9 MSR-Bitmap Address
24.6.10 Executive-VMCS Pointer
24.6.11 Extended-Page-Table Pointer (EPTP)
24.6.12 Virtual-Processor Identifier (VPID)
24.6.13 Controls for PAUSE-Loop Exiting
24.6.14 VM-Function Controls
24.6.15 VMCS Shadowing Bitmap Addresses
24.6.16 ENCLS-Exiting Bitmap
24.6.17 ENCLV-Exiting Bitmap
24.6.18 Control Field for Page-Modification Logging
24.6.19 Controls for Virtualization Exceptions
24.6.20 XSS-Exiting Bitmap
24.6.21 Sub-Page-Permission-Table Pointer (SPPTP)
24.7 VM-Exit Control Fields
24.7.1 VM-Exit Controls
24.7.2 VM-Exit Controls for MSRs
24.8 VM-Entry Control Fields
24.8.1 VM-Entry Controls
24.8.2 VM-Entry Controls for MSRs
24.8.3 VM-Entry Controls for Event Injection
24.9 VM-Exit Information Fields
24.9.1 Basic VM-Exit Information
24.9.2 Information for VM Exits Due to Vectored Events
24.9.3 Information for VM Exits That Occur During Event Delivery
24.9.4 Information for VM Exits Due to Instruction Execution
24.9.5 VM-Instruction Error Field
24.10 VMCS Types: Ordinary and Shadow
24.11 Software Use of the VMCS and Related Structures
24.11.1 Software Use of Virtual-Machine Control Structures
24.11.2 VMREAD, VMWRITE, and Encodings of VMCS Fields
24.11.3 Initializing a VMCS
24.11.4 Software Access to Related Structures
24.11.5 VMXON Region
21. Updates to Chapter 25, Volume 3C
Chapter 25 VMX Non-Root Operation
25.1 Instructions That Cause VM Exits
25.1.1 Relative Priority of Faults and VM Exits
25.1.2 Instructions That Cause VM Exits Unconditionally
25.1.3 Instructions That Cause VM Exits Conditionally
25.2 Other Causes of VM Exits
25.3 Changes to Instruction Behavior in VMX Non-Root Operation
25.4 Other Changes in VMX Non-Root Operation
25.4.1 Event Blocking
25.4.2 Treatment of Task Switches
25.5 Features Specific to VMX Non-Root Operation
25.5.1 VMX-Preemption Timer
25.5.2 Monitor Trap Flag
25.5.3 Translation of Guest-Physical Addresses Using EPT
25.5.4 Translation of Guest-Physical Addresses Used by Intel Processor Trace
25.5.4.1 Guest-Physical Address Translation for Intel PT: Details
25.5.4.2 Trace-Address Pre-Translation (TAPT)
25.5.5 APIC Virtualization
25.5.6 VM Functions
25.5.6.1 Enabling VM Functions
25.5.6.2 General Operation of the VMFUNC Instruction
25.5.6.3 EPTP Switching
25.5.7 Virtualization Exceptions
25.5.7.1 Convertible EPT Violations
25.5.7.2 Virtualization-Exception Information
25.5.7.3 Delivery of Virtualization Exceptions
25.6 Unrestricted Guests
22. Updates to Chapter 26, Volume 3C
Chapter 26 VM Entries
26.1 Basic VM-Entry Checks
26.2 Checks on VMX Controls and Host-State Area
26.2.1 Checks on VMX Controls
26.2.1.1 VM-Execution Control Fields
26.2.1.2 VM-Exit Control Fields
26.2.1.3 VM-Entry Control Fields
26.2.2 Checks on Host Control Registers, MSRs, and SSP
26.2.3 Checks on Host Segment and Descriptor-Table Registers
26.2.4 Checks Related to Address-Space Size
26.3 Checking and Loading Guest State
26.3.1 Checks on the Guest State Area
26.3.1.1 Checks on Guest Control Registers, Debug Registers, and MSRs
26.3.1.2 Checks on Guest Segment Registers
26.3.1.3 Checks on Guest Descriptor-Table Registers
26.3.1.4 Checks on Guest RIP, RFLAGS, and SSP
26.3.1.5 Checks on Guest Non-Register State
26.3.1.6 Checks on Guest Page-Directory-Pointer-Table Entries
26.3.2 Loading Guest State
26.3.2.1 Loading Guest Control Registers, Debug Registers, and MSRs
26.3.2.2 Loading Guest Segment Registers and Descriptor-Table Registers
26.3.2.3 Loading Guest RIP, RSP, RFLAGS, and SSP
26.3.2.4 Loading Page-Directory-Pointer-Table Entries
26.3.2.5 Updating Non-Register State
26.3.3 Clearing Address-Range Monitoring
26.4 Loading MSRs
26.5 Trace-Address Pre-Translation (TAPT)
26.6 Event Injection
26.6.1 Vectored-Event Injection
26.6.1.1 Details of Vectored-Event Injection
26.6.1.2 VM Exits During Event Injection
26.6.1.3 Event Injection for VM Entries to Real-Address Mode
26.6.2 Injection of Pending MTF VM Exits
26.7 Special Features of VM Entry
26.7.1 Interruptibility State
26.7.2 Activity State
26.7.3 Delivery of Pending Debug Exceptions after VM Entry
26.7.4 VMX-Preemption Timer
26.7.5 Interrupt-Window Exiting and Virtual-Interrupt Delivery
26.7.6 NMI-Window Exiting
26.7.7 VM Exits Induced by the TPR Threshold
26.7.8 Pending MTF VM Exits
26.7.9 VM Entries and Advanced Debugging Features
26.8 VM-Entry Failures During or After Loading Guest State
26.9 Machine-Check Events During VM Entry
23. Updates to Chapter 27, Volume 3C
Chapter 27 VM Exits
27.1 Architectural State Before a VM Exit
27.2 Recording VM-Exit Information and Updating VM-Entry Control Fields
27.2.1 Basic VM-Exit Information
27.2.2 Information for VM Exits Due to Vectored Events
27.2.3 Information About NMI Unblocking Due to IRET
27.2.4 Information for VM Exits During Event Delivery
27.2.5 Information for VM Exits Due to Instruction Execution
27.3 Saving Guest State
27.3.1 Saving Control Registers, Debug Registers, and MSRs
27.3.2 Saving Segment Registers and Descriptor-Table Registers
27.3.3 Saving RIP, RSP, RFLAGS, and SSP
27.3.4 Saving Non-Register State
27.4 Saving MSRs
27.5 Loading Host State
27.5.1 Loading Host Control Registers, Debug Registers, MSRs
27.5.2 Loading Host Segment and Descriptor-Table Registers
27.5.3 Loading Host RIP, RSP, RFLAGS, and SSP
27.5.4 Checking and Loading Host Page-Directory-Pointer-Table Entries
27.5.5 Updating Non-Register State
27.5.6 Clearing Address-Range Monitoring
27.6 Loading MSRs
27.7 VMX Aborts
27.8 Machine-Check Events During VM Exit
24. Updates to Chapter 32, Volume 3C
Chapter 32 Virtualization of System Resources
32.1 Overview
32.2 Virtualization Support for Debugging Facilities
32.2.1 Debug Exceptions
32.3 Memory Virtualization
32.3.1 Processor Operating Modes & Memory Virtualization
32.3.2 Guest & Host Physical Address Spaces
32.3.3 Virtualizing Virtual Memory by Brute Force
32.3.4 Alternate Approach to Memory Virtualization
32.3.5 Details of Virtual TLB Operation
32.3.5.1 Initialization of Virtual TLB
32.3.5.2 Response to Page Faults
32.3.5.3 Response to Uses of INVLPG
32.3.5.4 Response to CR3 Writes
32.4 Microcode Update Facility
32.4.1 Early Load of Microcode Updates
32.4.2 Late Load of Microcode Updates
25. Updates to Chapter 34, Volume 3C
Chapter 34 System Management Mode
34.1 System Management Mode Overview
34.1.1 System Management Mode and VMX Operation
34.2 System Management Interrupt (SMI)
34.3 Switching Between SMM and the Other Processor Operating Modes
34.3.1 Entering SMM
34.3.2 Exiting From SMM
34.4 SMRAM
34.4.1 SMRAM State Save Map
34.4.1.1 SMRAM State Save Map and Intel 64 Architecture
34.4.2 SMRAM Caching
34.4.2.1 System Management Range Registers (SMRR)
34.5 SMI Handler Execution Environment
34.5.1 Initial SMM Execution Environment
34.5.2 SMI Handler Operating Mode Switching
34.5.3 Control-flow Enforcement Technology Interactions
34.6 Exceptions and Interrupts Within SMM
34.7 Managing Synchronous and Asynchronous System Management Interrupts
34.7.1 I/O State Implementation
34.8 NMI Handling While in SMM
34.9 SMM Revision Identifier
34.10 Auto HALT Restart
34.10.1 Executing the HLT Instruction in SMM
34.11 SMBASE Relocation
34.12 I/O Instruction Restart
34.12.1 Back-to-Back SMI Interrupts When I/O Instruction Restart Is Being Used
34.13 SMM Multiple-Processor Considerations
34.14 Default Treatment of SMIs and SMM with VMX Operation and SMX Operation
34.14.1 Default Treatment of SMI Delivery
34.14.2 Default Treatment of RSM
34.14.3 Protection of CR4.VMXE in SMM
34.14.4 VMXOFF and SMI Unblocking
34.15 Dual-Monitor Treatment of SMIs and SMM
34.15.1 Dual-Monitor Treatment Overview
34.15.2 SMM VM Exits
34.15.2.1 Architectural State Before a VM Exit
34.15.2.2 Updating the Current-VMCS and Executive-VMCS Pointers
34.15.2.3 Recording VM-Exit Information
34.15.2.4 Saving Guest State
34.15.2.5 Updating State
34.15.3 Operation of the SMM-Transfer Monitor
34.15.4 VM Entries that Return from SMM
34.15.4.1 Checks on the Executive-VMCS Pointer Field
34.15.4.2 Checks on VM-Execution Control Fields
34.15.4.3 Checks on VM-Entry Control Fields
34.15.4.4 Checks on the Guest State Area
34.15.4.5 Loading Guest State
34.15.4.6 VMX-Preemption Timer
34.15.4.7 Updating the Current-VMCS and SMM-Transfer VMCS Pointers
34.15.4.8 VM Exits Induced by VM Entry
34.15.4.9 SMI Blocking
34.15.4.10 Failures of VM Entries That Return from SMM
34.15.5 Enabling the Dual-Monitor Treatment
34.15.6 Activating the Dual-Monitor Treatment
34.15.6.1 Initial Checks
34.15.6.2 Updating the Current-VMCS and Executive-VMCS Pointers
34.15.6.3 Saving Guest State
34.15.6.4 Saving MSRs
34.15.6.5 Loading Host State
34.15.6.6 Loading MSRs
34.15.7 Deactivating the Dual-Monitor Treatment
34.16 SMI and Processor Extended State Management
34.17 Model-Specific System Management Enhancement
34.17.1 SMM Handler Code Access Control
34.17.2 SMI Delivery Delay Reporting
34.17.3 Blocked SMI Reporting
26. Updates to Chapter 35, Volume 3C
Chapter 35 Intel® Processor Trace
35.1 Overview
35.1.1 Features and Capabilities
35.1.1.1 Packet Summary
35.2 Intel® Processor Trace Operational Model
35.2.1 Change of Flow Instruction (COFI) Tracing
35.2.1.1 Direct Transfer COFI
35.2.1.2 Indirect Transfer COFI
35.2.1.3 Far Transfer COFI
35.2.2 Software Trace Instrumentation with PTWRITE
35.2.3 Power Event Tracing
35.2.4 Trace Filtering
35.2.4.1 Filtering by Current Privilege Level (CPL)
35.2.4.2 Filtering by CR3
35.2.4.3 Filtering by IP
35.2.5 Packet Generation Enable Controls
35.2.5.1 Packet Enable (PacketEn)
35.2.5.2 Trigger Enable (TriggerEn)
35.2.5.3 Context Enable (ContextEn)
35.2.5.4 Branch Enable (BranchEn)
35.2.5.5 Filter Enable (FilterEn)
35.2.6 Trace Output
35.2.6.1 Single Range Output
35.2.6.2 Table of Physical Addresses (ToPA)
Single Output Region ToPA Implementation
ToPA Table Entry Format
ToPA STOP
ToPA PMI
PMI Preservation
ToPA PMI and Single Output Region ToPA Implementation
ToPA PMI and XSAVES/XRSTORS State Handling
ToPA Errors
35.2.6.3 Trace Transport Subsystem
35.2.6.4 Restricted Memory Access
Modifications to Restricted Memory Regions
35.2.7 Enabling and Configuration MSRs
35.2.7.1 General Considerations
35.2.7.2 IA32_RTIT_CTL MSR
35.2.7.3 Enabling and Disabling Packet Generation with TraceEn
Disabling Packet Generation
Other Writes to IA32_RTIT_CTL
35.2.7.4 IA32_RTIT_STATUS MSR
35.2.7.5 IA32_RTIT_ADDRn_A and IA32_RTIT_ADDRn_B MSRs
35.2.7.6 IA32_RTIT_CR3_MATCH MSR
35.2.7.7 IA32_RTIT_OUTPUT_BASE MSR
35.2.7.8 IA32_RTIT_OUTPUT_MASK_PTRS MSR
35.2.8 Interaction of Intel® Processor Trace and Other Processor Features
35.2.8.1 Intel® Transactional Synchronization Extensions (Intel® TSX)
35.2.8.2 TSX and IP Filtering
35.2.8.3 System Management Mode (SMM)
35.2.8.4 Virtual-Machine Extensions (VMX)
35.2.8.5 Intel® Software Guard Extensions (Intel® SGX)
35.2.8.6 SENTER/ENTERACCS and ACM
35.2.8.7 Intel® Memory Protection Extensions (Intel® MPX)
35.3 Configuration and programming Guideline
35.3.1 Detection of Intel Processor Trace and Capability Enumeration
35.3.1.1 Packet Decoding of RIP versus LIP
35.3.1.2 Model Specific Capability Restrictions
35.3.2 Enabling and Configuration of Trace Packet Generation
35.3.2.1 Enabling Packet Generation
35.3.2.2 Disabling Packet Generation
35.3.3 Flushing Trace Output
35.3.4 Warm Reset
35.3.5 Context Switch Consideration
35.3.5.1 Manual Trace Configuration Context Switch
35.3.5.2 Trace Configuration Context Switch Using XSAVES/XRSTORS
35.3.6 Cycle-Accurate Mode
35.3.6.1 Cycle Counter
35.3.6.2 Cycle Packet Semantics
35.3.6.3 Cycle Thresholds
35.3.7 Decoder Synchronization (PSB+)
35.3.8 Internal Buffer Overflow
35.3.8.1 Overflow Impact on Enables
35.3.8.2 Overflow Impact on Timing Packets
35.3.9 Operational Errors
35.4 Trace Packets and Data Types
35.4.1 Packet Relationships and Ordering
35.4.1.1 Packet Blocks
Decoder Implications
35.4.2 Packet Definitions
35.4.2.1 Taken/Not-taken (TNT) Packet
35.4.2.2 Target IP (TIP) Packet
IP Compression
Indirect Transfer Compression for Returns (RET)
35.4.2.3 Deferred TIPs
35.4.2.4 Packet Generation Enable (TIP.PGE) Packet
35.4.2.5 Packet Generation Disable (TIP.PGD) Packet
35.4.2.6 Flow Update (FUP) Packet
FUP IP Payload
35.4.2.7 Paging Information (PIP) Packet
35.4.2.8 MODE Packets
MODE.Exec Packet
MODE.TSX Packet
35.4.2.9 TraceStop Packet
35.4.2.10 Core:Bus Ratio (CBR) Packet
35.4.2.11 Timestamp Counter (TSC) Packet
35.4.2.12 Mini Time Counter (MTC) Packet
35.4.2.13 TSC/MTC Alignment (TMA) Packet
35.4.2.14 Cycle Count (CYC) Packet
35.4.2.15 VMCS Packet
35.4.2.16 Overflow (OVF) Packet
35.4.2.17 Packet Stream Boundary (PSB) Packet
35.4.2.18 PSBEND Packet
35.4.2.19 Maintenance (MNT) Packet
35.4.2.20 PAD Packet
35.4.2.21 PTWRITE (PTW) Packet
35.4.2.22 Execution Stop (EXSTOP) Packet
35.4.2.23 MWAIT Packet
35.4.2.24 Power Entry (PWRE) Packet
35.4.2.25 Power Exit (PWRX) Packet
35.4.2.26 Block Begin Packet (BBP)
35.4.2.27 Block Item Packet (BIP)
BIP State Value Encodings
35.4.2.28 Block End Packet (BEP)
35.5 Tracing in VMX Operation
35.5.1 VMX-Specific Packets and VMCS Controls
35.5.2 Managing Trace Packet Generation Across VMX Transitions
35.5.2.1 System-Wide Tracing
35.5.2.2 Guest-Only Tracing
35.5.2.3 Emulation of Intel PT Traced State
35.5.2.4 TSC Scaling
35.5.2.5 Failed VM Entry
35.5.2.6 VMX Abort
35.6 Tracing and SMM Transfer Monitor (STM)
35.7 Packet Generation Scenarios
35.8 Software Considerations
35.8.1 Tracing SMM Code
35.8.2 Cooperative Transition of Multiple Trace Collection Agents
35.8.3 Tracking Time
35.8.3.1 Time Domain Relationships
35.8.3.2 Estimating TSC within Intel PT
35.8.3.3 VMX TSC Manipulation
35.8.3.4 Calculating Frequency with Intel PT
27. Updates to Chapter 40, Volume 3D
Chapter 40 SGX Instruction References
40.1 Intel® SGX Instruction Syntax and Operation
40.1.1 ENCLS Register Usage Summary
40.1.2 ENCLU Register Usage Summary
40.1.3 ENCLV Register Usage Summary
40.1.4 Information and Error Codes
40.1.5 Internal CREGs
40.1.6 Concurrent Operation Restrictions
40.1.6.1 Concurrency Tables of Intel® SGX Instructions
40.2 Intel® SGX Instruction Reference
ENCLS—Execute an Enclave System Function of Specified Leaf Number
ENCLU—Execute an Enclave User Function of Specified Leaf Number
ENCLV—Execute an Enclave VMM Function of Specified Leaf Number
40.3 Intel® SGX System Leaf Function Reference
EADD—Add a Page to an Uninitialized Enclave
EAUG—Add a Page to an Initialized Enclave
EBLOCK—Mark a page in EPC as Blocked
ECREATE—Create an SECS page in the Enclave Page Cache
EDBGRD—Read From a Debug Enclave
EDBGWR—Write to a Debug Enclave
EEXTEND—Extend Uninitialized Enclave Measurement by 256 Bytes
EINIT—Initialize an Enclave for Execution
ELDB/ELDU/ELDBC/ELDUC—Load an EPC Page and Mark its State
EMODPR—Restrict the Permissions of an EPC Page
EMODT—Change the Type of an EPC Page
EPA—Add Version Array
ERDINFO—Read Type and Status Information About an EPC Page
EREMOVE—Remove a page from the EPC
ETRACK—Activates EBLOCK Checks
ETRACKC—Activates EBLOCK Checks
EWB—Invalidate an EPC Page and Write out to Main Memory
40.4 Intel® SGX User Leaf Function Reference
EACCEPT—Accept Changes to an EPC Page
EACCEPTCOPY—Initialize a Pending Page
EENTER—Enters an Enclave
EEXIT—Exits an Enclave
EGETKEY—Retrieves a Cryptographic Key
EMODPE—Extend an EPC Page Permissions
EREPORT—Create a Cryptographic Report of the Enclave
ERESUME—Re-Enters an Enclave
40.5 Intel® SGX Virtualization Leaf Function Reference
EDECVIRTCHILD—Decrement VIRTCHILDCNT in SECS
EINCVIRTCHILD—Increment VIRTCHILDCNT in SECS
ESETCONTEXT—Set the ENCLAVECONTEXT Field in SECS
28. Updates to Chapter 42, Volume 3D
Chapter 42 Enclave Code Debug and Profiling
42.1 Configuration and Controls
42.1.1 Debug Enclave vs. Production Enclave
42.1.2 Tool-Chain Opt-in
42.2 Single Step Debug
42.2.1 Single Stepping ENCLS Instruction Leafs
42.2.2 Single Stepping ENCLU Instruction Leafs
42.2.3 Single-Stepping Enclave Entry with Opt-out Entry
42.2.3.1 Single Stepping without AEX
42.2.3.2 Single Step Preempted by AEX Due to Non-SMI Event
42.2.4 RFLAGS.TF Treatment on AEX
42.2.5 Restriction on Setting of TF after an Opt-Out Entry
42.2.6 Trampoline Code Considerations
42.3 Code and Data Breakpoints
42.3.1 Breakpoint Suppression
42.3.2 Reporting of Instruction Breakpoint on Next Instruction on a Debug Trap
42.3.3 RF Treatment on AEX
42.3.4 Breakpoint Matching in Intel® SGX Instruction Flows
42.4 Consideration of the INT1 and INT3 Instructions
42.4.1 Behavior of INT1 and INT3 Inside an Enclave
42.4.2 Debugger Considerations
42.4.3 VMM Considerations
42.5 Branch Tracing
42.5.1 BTF Treatment
42.5.2 LBR Treatment
42.5.2.1 LBR Stack on Opt-in Entry
42.5.2.2 LBR Stack on Opt-out Entry
42.5.2.3 Mispredict Bit, Record Type, and Filtering
42.6 Interaction with Performance Monitoring
42.6.1 IA32_PERF_GLOBAL_STATUS Enhancement
42.6.2 Performance Monitoring with Opt-in Entry
42.6.3 Performance Monitoring with Opt-out Entry
42.6.4 Enclave Exit and Performance Monitoring
42.6.5 PEBS Record Generation on Intel® SGX Instructions
42.6.6 Exception-Handling on PEBS/BTS Loads/Stores after AEX
42.6.6.1 Other Interactions with Performance Monitoring
29. Updates to Appendix C, Volume 3D
Appendix C VMX Basic Exit Reasons
30. Updates to Chapter 1, Volume 4
Chapter 1 About This Manual
1.1 Intel® 64 and IA-32 Processors Covered in this Manual
1.2 Overview of The SYSTEM PROGRAMMING GUIDE
1.3 Notational Conventions
1.3.1 Bit and Byte Order
1.3.2 Reserved Bits and Software Compatibility
1.3.3 Instruction Operands
1.3.4 Hexadecimal and Binary Numbers
1.3.5 Segmented Addressing
1.3.6 Syntax for CPUID, CR, and MSR Values
1.3.7 Exceptions
1.4 Related Literature
31. Updates to Chapter 2, Volume 4
Chapter 2 Model-Specific Registers (MSRs)
2.1 Architectural MSRs
2.2 MSRs In the Intel® Core™ 2 Processor Family
2.3 MSRs In the 45 nm and 32 nm Intel Atom® Processor Family
2.4 MSRs In Intel Processors Based on Silvermont Microarchitecture
2.4.1 MSRs with Model-Specific Behavior in the Silvermont Microarchitecture
2.4.2 MSRs In Intel Atom® Processors Based on Airmont Microarchitecture
2.5 MSRs In Intel Atom® Processors based on Goldmont Microarchitecture
2.6 MSRs In Intel Atom® Processors Based on Goldmont Plus Microarchitecture
2.7 MSRs In Intel Atom® Processors Based on Tremont Microarchitecture
2.8 MSRs In the Intel® Microarchitecture Code Name Nehalem
2.8.1 Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series
2.8.2 Additional MSRs in the Intel® Xeon® Processor 7500 Series
2.9 MSRs In the Intel® Xeon® Processor 5600 Series (Based on Intel® Microarchitecture Code Name Westmere)
2.10 MSRs In the Intel® Xeon® Processor E7 Family (Based on Intel® Microarchitecture Code Name Westmere)
2.11 MSRs In Intel® Processor Family Based on Intel® Microarchitecture Code Name Sandy Bridge
2.11.1 MSRs In 2nd Generation Intel® Core™ Processor Family (Based on Intel® Microarchitecture Code Name Sandy Bridge)
2.11.2 MSRs In Intel® Xeon® Processor E5 Family (Based on Intel® Microarchitecture Code Name Sandy Bridge)
2.11.3 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 Family
2.12 MSRs In the 3rd Generation Intel® Core™ Processor Family (Based on Intel® microarchitecture code name Ivy Bridge)
2.12.1 MSRs In Intel® Xeon® Processor E5 v2 Product Family (Based on Ivy Bridge-E Microarchitecture)
2.12.2 Additional MSRs Supported by Intel® Xeon® Processor E7 v2 Family
2.12.3 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families
2.13 MSRs In the 4th Generation Intel® Core™ Processors (Based on Haswell Microarchitecture)
2.13.1 MSRs in 4th Generation Intel® Core™ Processor Family (based on Haswell Microarchitecture)
2.13.2 Additional Residency MSRs Supported in 4th Generation Intel® Core™ Processors
2.14 MSRs In Intel® Xeon® Processor E5 v3 and E7 v3 Product Family
2.14.1 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family
2.15 MSRs In Intel® Core™ M Processors and 5th Generation Intel Core Processors
2.16 MSRs In Intel® Xeon® Processors E5 v4 Family
2.16.1 Additional MSRs Supported in the Intel® Xeon® Processor D Product Family
2.16.2 Additional MSRs Supported in Intel® Xeon® Processors E5 v4 and E7 v4 Families
2.17 MSRs In the 6th Generation, 7th Generation, 8th Generation, 9th Generation, 10th Generation, and 11th Generation Intel® Core™ Processors, Intel® Xeon® Processor Scalable Family, 8th Generation Intel® Core™ i3 Processors, and Intel® Xeon...
2.17.1 MSRs Specific to 7th Generation and 8th Generation Intel® Core™ Processors based on Kaby Lake Microarchitecture and Coffee Lake Microarchitecture
2.17.2 MSRs Specific to 8th Generation Intel® Core™ i3 Processors
2.17.3 MSRs Specific to 10th Generation Intel® Core™ Processors
2.17.4 MSRs Specific to 11th Generation Intel® Core™ Processors based on Tiger Lake Microarchitecture
2.17.5 MSRs Specific to Intel® Xeon® Processor Scalable Family
2.18 MSRs In Intel® Xeon Phi™ Processor 3200/5200/7200 Series and Intel® Xeon Phi™ Processor 7215/7285/7295 Series
2.19 MSRs In the Pentium® 4 and Intel® Xeon® Processors
2.19.1 MSRs Unique to Intel® Xeon® Processor MP with L3 Cache
2.20 MSRs In Intel® Core™ Solo and Intel® Core™ Duo Processors
2.21 MSRs In the Pentium M Processor
2.22 MSRs In the P6 Family Processors
2.23 MSRs in Pentium Processors
2.24 MSR Index