✦ LIBER ✦

Improvements to Technology Mapping for LUT-Based FPGAs

✍ Scribed by Mishchenko, A.; Chatterjee, S.; Brayton, R. K.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Heuristics for Area Minimization in LUT-

✍ Manohararajah, V.; Brown, S.D.; Vranesic, Z.G. 📂 Article 📅 2006 🏛 IEEE 🌐 English ⚖ 521 KB

LUT-based FPGA technology mapping under

✍ Jason Cong; Yuzheng Ding; Tong Gao; Kuang-Chien Chen 📂 Article 📅 1994 🏛 Elsevier Science 🌐 English ⚖ 860 KB

KGPMAP:library-based technology-mapping

✍ Chattopadhyay, S.; Roy, S.; Pal Chaudhuri, P. 📂 Article 📅 1994 🏛 The Institution of Electrical Engineers 🌐 English ⚖ 749 KB

KGPMAP: library-based technology-mapping

✍ Falkowski, B.J. 📂 Article 📅 1996 🏛 The Institution of Electrical Engineers 🌐 English ⚖ 205 KB

Optimality Study of Logic Synthesis for

✍ Cong, J.; Minkovich, K. 📂 Article 📅 2007 🏛 IEEE 🌐 English ⚖ 896 KB

Direct mapping of RTL structures onto LU

✍ Naseer, A.R.; Balakrishnan, M.; Kumar, A. 📂 Article 📅 1998 🏛 IEEE 🌐 English ⚖ 233 KB