This paper uses a CAD methodology proposed by the authors to design a low-power second-order M. This modulator has been fabricated in a 0•7 m CMOS technology to be used as the front-end of an energy-metering mixed-signal ASIC and features 16•4 bit at a digital output rate of 9•6 kHz with a power con
✦ LIBER ✦
Improved technique used in high performance balanced vector modulators design
✍ Scribed by Yang Hou; Lingyun Li; Xiaowei Sun
- Publisher
- John Wiley and Sons
- Year
- 2008
- Tongue
- English
- Weight
- 310 KB
- Volume
- 50
- Category
- Article
- ISSN
- 0895-2477
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✦ Synopsis
Abstract
This article describes and analyses an improved technique for the realization of balanced vector modulators. The analysis focuses on the effect of the Lange coupler characteristic impedance and the pHEMT total gate width on the modulator minimum insertion loss. A method of adjusting these parameters to optimum values is used to reduce the loss and achieve a more symmetrical constellation. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 2325–2328, 2008; Published online in Wiley InterScience (www.interscience.wiley.com).DOI 10.1002/mop.23682
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