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Implementation of the prodigy parallel AI machine and performance evaluation of communication

✍ Scribed by Noboru Tanabe; Sadao Nakamura; Takashi Suzuoka; Shigeru Oyanagi


Publisher
John Wiley and Sons
Year
1992
Tongue
English
Weight
935 KB
Volume
23
Category
Article
ISSN
0882-1666

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✦ Synopsis


Abstract

At present, the binary n‐cube is considered to be interesting as an interconnection network for the highly parallel computers. Most of those networks, however, use the serial communication channel, which prevents the realization of satisfactory communication performance. From such a viewpoint, it is desired to construct an interconnection network with higher speed, higher versatility, and the easy implementation.

The authors have already proposed the base‐m n‐cube as the interconnection network for the parallel AI machine Prodigy. This paper shows that the base‐m n‐cube is better than the binary n‐cube in versatility and easy implementation. Furthermore, the authors developed Prodigy which utilizes the forementioned excellent property to connect 512 processors by the 8‐bit width full duplex base‐8 3‐cube with a handshake. Two kinds of gate arrays are used in the implementation. It is shown as a result that the interconnection network can be constructed with the highest speed in the presently known cube‐type highly parallel computers. It is verified by an actual measurement that the transfer performance is deteriorated only slightly by the collision in the random communication.


πŸ“œ SIMILAR VOLUMES


Implementation and evaluation of improve
✍ Takafumi Fukunaga; Hidenori Umeno πŸ“‚ Article πŸ“… 2010 πŸ› Wiley (John Wiley & Sons) 🌐 English βš– 522 KB

## Abstract Various techniques that improve performance on SMP clusters have been studied. Most of them use special hardware and nonstandard protocols, tending to raise their total cost and to spoil flexibility. We propose the CPU\_NIC method, which improves parallel performance on small‐way SMP PC