Implementation and evaluation of improvement in parallel processing performance on the cluster using small-scale SMP PCs
✍ Scribed by Takafumi Fukunaga; Hidenori Umeno
- Publisher
- Wiley (John Wiley & Sons)
- Year
- 2010
- Tongue
- English
- Weight
- 522 KB
- Volume
- 93
- Category
- Article
- ISSN
- 1942-9533
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✦ Synopsis
Abstract
Various techniques that improve performance on SMP clusters have been studied. Most of them use special hardware and nonstandard protocols, tending to raise their total cost and to spoil flexibility. We propose the CPU_NIC method, which improves parallel performance on small‐way SMP PC clusters by simply loading a driver. The proposed system could be implemented with nonintelligent switches. The proposed method uses the same number of NICs as CPUs and relates the CPUs and NICs on a one‐to‐one basis. The frames are transmitted from the NIC associated with the execution CPU number. Thus, by fixing the transmitting NIC for every CPU, the number of SACK frames, that are easily generated in communication load sharing to two or more NICs, can be reduced and parallel application performance can be improved. The NPB Benchmark of four cluster PCs indicated that FT, MG, and CG were faster by factors of 1.12, 1.29, and 3.06, respectively, under the proposed method than in an ordinary system without this method. © 2010 Wiley Periodicals, Inc. Electron Comm Jpn, 93(10): 1–11, 2010; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/ecj.10315