Implementation of Petri nets using a field-programmable gate array

✍ Scribed by S. K. Yang; T. S. Liu

• Publisher: John Wiley and Sons
• Year: 2000
• Tongue: English
• Weight: 507 KB
• Volume: 16
• Category: Article
• ISSN: 0748-8017
• DOI: 10.1002/(sici)1099-1638(200003/04)16:2<99::aid-qre308>3.0.co;2-j

✦ Synopsis

Although Petri nets have various capabilities, the Petri net approach is done on paper. A field-programmable gate array (FPGA) is implemented in this study so as to realize basic Petri net symbols, logic structures in Petri nets, and specific functions for Petri nets by logic circuits. As an example, a Petri net for an early failure detection and isolation arrangement (EFDIA) is implemented as an application-specific integrated circuit (ASIC) on a Xilinx Demonstration Board. This ASIC is verified by three simulations dealing with three different failure scenarios of a system, and the ASIC functions identically to the EFDIA Petri net. Accordingly, not only the EFDIA Petri net but also any specific function Petri nets can be implemented by FPGA circuits.