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Implementation of a high speed Fast Fourier Transform VLSI chip

✍ Scribed by S.A Samad; A Ragoub; M Othman; Z.A.M Shariff

Publisher: Elsevier Science
Year: 1998
Tongue: English
Weight: 380 KB
Volume: 29
Category: Article
ISSN: 0026-2692
DOI: 10.1016/s0026-2692(98)00048-2

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✦ Synopsis

Very high speed proce,;sing of radar signals has led to the requirement of very high speed conversion of signals from the time domain to the frequency domain. In this paper we discuss the implementation of an FFT chip based on the proposed digit slicing architecture. The paper begins with a discussion of the digit slicing technique. This is followed by discussions on the basic building blocks of the digit slicing FFT and implementation of a prototype digit slicing FFT using DSP station. The paper is concluded by comparing the speed and other properties of the unsliced FFT and digit slicing FFT architectures.

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