The impact of line-edge roughness (LER) on resistance R and capacitance C of on-chip interconnects is for the first time evaluated by a simulation methodology based on a realistic modeling of LER. The model can be calibrated with measured LER parameters. A geometrical approximations of LER is genera
β¦ LIBER β¦
Impact of the surface roughness on the electrical capacitance
β Scribed by A. Albina; P.L. Taberna; J.P. Cambronne; P. Simon; E. Flahaut; T. Lebey
- Publisher
- Elsevier Science
- Year
- 2006
- Tongue
- English
- Weight
- 395 KB
- Volume
- 37
- Category
- Article
- ISSN
- 0026-2692
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