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Impact of clock slope on true single phase clocked (TSPC) CMOS circuits

โœ Scribed by Larsson, P.; Svensson, C.


Book ID
119774024
Publisher
IEEE
Year
1994
Tongue
English
Weight
338 KB
Volume
29
Category
Article
ISSN
0018-9200

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A comparative study of glitch-free true
โœ Hanho Lee; Gerald E. Sobelman ๐Ÿ“‚ Article ๐Ÿ“… 1998 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 468 KB

This paper investigates the characteristics and performances of several true single-phase clocked (TSPC) D flip-flops (D-FFs) at low supply voltage. We propose a new glitch-free D-FF for low-voltage operation. Since the dynamic power consumption in CMOS is proportional to V~d, decreasing the supply