Based on the reconfigurable array of processors with wider bus networks, we propose a series of algorithms for image processing. Conventionally, only one bus is connected between two processors but in this machine it has a set of buses. Such a characteristic increases the computation power of this m
โฆ LIBER โฆ
Image component labeling on reconfigurable processor array
โ Scribed by M Maresca; P Baglietto; A Giordano
- Publisher
- Elsevier Science
- Year
- 1993
- Weight
- 592 KB
- Volume
- 38
- Category
- Article
- ISSN
- 0165-6074
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