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[IEEE Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. - Napa Valley, CA, USA (Nov. 30-Dec. 2, 2005)] Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. - VERISEC: VERIfying equivalence of SEquential Circuits using SAT

✍ Scribed by Syal, M.; Hsiao, M.S.

Book ID: 126671384
Publisher: IEEE
Year: 2005
Weight: 201 KB
Category: Article
ISBN-13: 9780780395718
DOI: 10.1109/HLDVT.2005.1568813

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