[IEEE Design, Automation & Test in Europe Conference - Nice, France (2007.04.16-2007.04.20)] 2007 Design, Automation & Test in Europe Conference & Exhibition - Joint Consideration of Fault-Tolerance, Energy-Efficiency and Performance in On-Chip Networks

✍ Scribed by Ejlali, Alireza; Al-Hashimi, Bashir M.; Rosinger, Paul; Miremadi, Seyed Ghassem

• Book ID: 118057534
• Publisher: IEEE
• Year: 2007
• Tongue: German
• Weight: 244 KB
• Volume: 0
• Category: Article
• ISBN: 3981080122
• DOI: 10.1109/date.2007.364538

✦ Synopsis

High reliability against noise, low energy consumption and high performance are key objectives in the design of on-chip networks. Recently some researchers have considered the various trade-offs between two of these objectives. However, as we will argue later, the three design objectives should be considered jointly and simultaneously. The first aim of this paper is to analyze the impact of various error-control schemes on the simultaneous trade-off between reliability, performance and energy when voltage swing varies. We provide a detailed comparative analysis of the error-control schemes using analytical models and SPICE simulations. The second aim of this paper is to analyze the impact of noise power and time constraint on the effectiveness of errorcontrol schemes, which have not been addressed in previous studies.